CDCE62005 datasheet(45/76 Pages) TI

45 / 76 page

OutputDivider (7-bits)

DigitalPhase Adjust (7-bits)

Sync

Pulse

(internallygenerated )

Enable

From

Output

MUX

Output

Buffer

Registers 0 - 4

/2-/5

/1 - /8

From

Output

MUX

Output

Buffer

Registers 0 - 4

Prescaler

IntegerDivider

Registers 0 - 4

CDCE62005

www.ti.com........................................................................................................................................................................................... SCAS862 – NOVEMBER 2008

Output Dividers

Figure 29 shows that each output channel provides a 7-bit divider and digital phase adjust block. Table 23 lists

the divide ratios supported by the output divider for each output channel. Figure 30 illustrates the output divider

architecture in detail. The Prescaler provides an array of low noise dividers with duty cycle correction. The

Integer Divider includes a final divide by two stage which is used to correct the duty cycle of the /1–/8 stage. The

output divider’s maximum input frequency is limited to 1.175GHz. If the divider is bypassed (divide ratio = 1) then

the maximum frequency of the output channel is 1.5GHz.

Figure 29. CDCE62005 Output Divider and Phase Adjust

Figure 30. CDCE62005 Output Divider Architecture

Submit Documentation Feedback

Product Folder Link(s) :CDCE62005

CDCE62005 Datasheet(PDF) 45 Page - Texas Instruments

CDCE62005 Datasheet(HTML) 45 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

Datasheet Download

Link URL