SLWS132 datasheet(43/46 Pages) TI

43 / 46 page

GRAYCHIP, INC.

- 38 -

APRIL 27, 1999

GC4014 QUAD RECEIVER CHIP

DATA SHEET REV 0.6

This document contains information which may be changed at any time without notice

7.8

OUTPUT TEST CONFIGURATION

The following configuration allows the user to debug the output interface to insure that the GC4014 data is

being received properly by the following circuitry. The configuration in the following table will generate a fixed output

sequence of four values (two complex pairs) which will repeat indefinitely:

The programmable PFIR coefficients are not used and do not need to be loaded. The user should change

address 6 (Output Format Register) to reflect the desired serial or link output mode. The expected results for various

decimation ratios are shown below:

The output sequence is the same for all power-of-two decimations. Other decimation ratios, with the SCALE

and BIG_SCALE values being the maximum which satisfy:

, will result in

sequences with the same I values, but with slightly different Q values.

Table 17: Output Test Conﬁguration

Control Registers

Channel pages 4,5,6,7

Address

Data

Address

Data

00 (HEX)

6A (HEX)1

10 (HEX)

00 (HEX)

0F2

002

632

113

0P4

read only

1. Initialize to 6A while configuring the chip(s), then set to EA, then back to 6A to fire off the one-shot sync.

2. Gives an overall decimate by 64, See Table 18 for other values.

3. Value is application dependent.

4. “P” is the page number. The upper nibble should stay at “0¨.

Table 18: Test Output Sequence

Decimation Controls

Output Sequence

Overall

Decimation

Addresses

2, 3

Address 4

07, 00

8000

FD00

7F00

0300

0F, 00

128

1F, 00

256

3F, 00

512

7F, 00

1024

FF, 00

2048

FF, 01

100

18, 00

8000

FE00

7F00

0200

SCALE

BIG_SCALE

()

4log

–

()

≤

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