SLWS132 datasheet(16/46 Pages) TI

16 / 46 page

GRAYCHIP, INC.

- 11 -

APRIL 27, 1999

GC4014 QUAD RECEIVER CHIP

DATA SHEET REV 0.6

This document contains information which may be changed at any time without notice

words will be transmitted immediately following the first I/Q pair as shown in Figure 10(c). Figure 10(c) also shows

how the RDY signal can be used to identify the I and Q channels in the TDM serial transmission.The bit-serial output

rate is programmable as a power-of-2 division of the input clock.

Figure 10. Serial Output Formats

The serial clock (SCK) will normally stop after the last bit transfer of each OSP. The user can force a

continuous clock by setting the CONTINUOUS control bit in the output control register. In the continuous mode the

data is repeated until the next OSP. This may be useful if the user wants to multiplex the outputs from multiple chips

onto the same serial bus. Note: The frame syncs are not intended to be used in the continuous mode. After the

proper number of frame syncs have been output as shown in Figure 10, the next frame sync will be missing in the

continuous mode. The frame syncs will then repeat every 16 (or 32 in the packed mode) bit clocks. Note also that

the number of bit clocks per output frame may not be a rational number, resulting in a truncated bit clock at the end

of the OSP.

3.6.3

Link Mode Output

The four serial output pins and the bit clock and frame sync pins can be configured as an ADSP-2106x

SHARC DSP chip link port. These pins are in a tri-state condition when the chip powers up. A control bit is set to

enable these pins and another control bit is set to enable the link port mode. In the link mode the READY output pin

becomes the ACK (acknowledge) input which is used to receive the link port “LACK” signal.

SCK

SFS

SOUT

I15

I14

Q15

Q14

(a) 16 BIT MODE, FRAME SYNC AT THE START OF EACH 16 BIT WORD

SCK

SFS

SOUT

I15

I14

Q15

Q14

(b) 32 BIT “PACKED” MODE, ONE FRAME SYNC AT THE START OF EACH 32 BIT TRANSFER

clock stops after transfers are complete and stays low unless “continuous” is set

RDY is 4 clocks wide (CK not SCK clocks) or is 16 clocks wide if RDY_WIDTH is set

RDY

SFS

SOUT

MUX_MODE=0

MUX_MODE=1

MUX_MODE=2

Output Sample Period (OSP)

I15

I14

The words repeat in the continuous mode

I15

I14

The words repeat in the continuous mode

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