TMS370 datasheet(6/66 Pages) TI

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TMS370Cx4x

8-BIT MICROCONTROLLER

SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

central processing unit (CPU)

The CPU used on the TMS370Cx4x device is the high-performance 8-bit TMS370 CPU module. The ’x4x

implements an efficient register-to-register architecture that eliminates the conventional accumulator

bottleneck. The complete ’x4x instruction map is shown in Table 17 in the TMS370Cx4x instruction set overview

section.

The ’370Cx4x CPU architecture provides the following components:

D CPU registers:

–

A stack pointer (SP) that points to the last entry in the memory stack

–

A status register (ST) that monitors the operation of the instructions and contains the

global-interrupt-enable bits

–

A program counter (PC) that points to the memory location of the next instruction to be executed

Figure 1 illustrates the CPU registers and memory blocks.

Reserved†

Peripheral File

Not Available‡

0FFFh

1000h

1F00h

1FFFh

2000h

5FFFh

6000h

Interrupts and Reset Vectors;

Trap Vectors

10FFh

1100h

1EFFh

Reserved†

7FFFh

RAM (Includes up to 256-Byte Registers File)

Program Counter

Legend:

Z=Zero

IE1=Level 1 interrupts Enable

C=Carry

V=Overflow

N=Negative

IE2=Level 2 interrupts Enable

IE1

IE2

Status Register (ST)

Stack Pointer (SP)

R0(A)

R1(B)

R127

0000h

0001h

0002h

007Fh

R255

0003h

00FFh

256-Byte Data EEPROM

6FFFh

7000h

8K-Byte ROM/EPROM (6000h – 6FFFh)

4K-Byte ROM (7000h – 7FFFh)

7FC0h

7FBFh

00FFh

0100h

256-Byte RAM (0000h–00FFh)

0000h

† Reserved means the address space is reserved for future expansion.

‡ Not available means the address space is not accessible.

Figure 1. Programmer’s Model

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