TMS370 datasheet(7/66 Pages) TI

7 / 66 page

TMS370Cx4x

8-BIT MICROCONTROLLER

SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

central processing unit (CPU) (continued)

D A memory map that includes:

–

256-byte general-purpose RAM that can be used for data memory storage, program instructions,

general-purpose registers, or the stack

–

A peripheral file that provides access to all internal peripheral modules, system-wide control functions

and EEPROM / EPROM programming control

–

256-byte EEPROM module that provides in-circuit programmability and data retention in power-off

conditions

–

4K- or 8K-byte ROM or 8K-byte EPROM program memory

stack pointer (SP)

The SP is an 8-bit CPU register. The stack operates as a last-in, first-out, read / write memory. The stack is used

typically to store the return address on subroutine calls as well as the status-register contents during interrupt

sequences.

The SP points to the last entry or top of the stack. The SP is incremented automatically before data is pushed

onto the stack and decremented after data is popped from the stack. The stack can be placed anywhere in the

on-chip RAM memory.

status register (ST)

The ST monitors the operation of the instructions and contains the global interrupt-enable bits. The ST includes

four status bits (condition flags) and two interrupt-enable bits:

D The four status bits indicate the outcome of the previous instruction; conditional instructions (for example,

the conditional jump instructions) use the status bits to determine program flow.

D The two interrupt-enable bits control the two interrupt levels.

The ST register, status-bit notation, and status-bit definitions are shown in Table 3.

Table 3. Status Registers

IE2

IE1

Reserved

RW-0

R = read, W = write, 0 = value after reset

program counter (PC)

The contents of the PC point to the memory location of the next instruction to be executed. The PC consists

of two 8-bit registers in the CPU: the program counter high (PCH) and program counter low (PCL). These

registers contain the most significant byte (MSbyte) and least significant byte (LSbyte) of a 16-bit address.

The contents of the reset vector (7FFEh, 7FFFh) are loaded into the program counter during reset. The PCH

(MSbyte of the PC) is loaded with the contents of memory location 7FFEh, and the PCL (LSbyte of the PC) is

loaded with the contents of memory location 7FFFh. Figure 2 shows this operation using an example value of

6000h as the contents of memory locations 7FFEh and 7FFFh (reset vector).

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