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TMS370 Datasheet(PDF) 32 Page - Texas Instruments

Part # TMS370
Description  8-BIT MICROCONTROLLER
PDF  66 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS370 Datasheet(HTML) 32 Page - Texas Instruments

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TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997
32
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
serial communications interface 1 (SCI1)
The TMS370Cx4x devices include a serial communications interface 1 (SCI1) module. The SCI1 module
supports digital communications between the TMS370 devices and other asynchronous peripherals and uses
the standard non return-to-zero format (NRZ) format. The SCI1’s receiver and transmitter are double buffered,
and each has its own separate enable and interrupt bits. Both can be operated independently or simultaneously
in the full duplex mode. To ensure data integrity, the SCI1 checks received data for break detection, parity,
overrun, and framing errors. The bit rate (baud) is programmable to over 65,000 different rates through a 16-bit
baud-select register.
Features of the SCI1 module include:
D Three external pins:
–
SCITXD: SCI transmit-output pin or general purpose bidirectional I/O pin.
–
SCIRXD: SCI receive-input pin or general purpose bidirectional I/O pin.
–
SCICLK: SCI bidirectional serial-clock pin, or general-purpose bidirectional I/O pin.
D Two communications modes: asynchronous and isosynchronous
D Baud rate: 64K different programmable rates
–
Asynchronous mode: 3 bps to 156K bps at 5 MHz SYSCLK
Asynchronous Baud
+
SYSCLK
(BAUD REG
) 1)
32
–
Isosynchronous mode: 39 bps to 2.5 Mbps at 5 MHz SYSCLK
Isosynchronous Baud
+
SYSCLK
(BAUD REG
) 1)
2
D Data word format:
–
One start bit
–
Data word length programmable from one to eight bits
–
Optional even / odd / no parity bit
–
One or two stop bits
D Four error-detection flags: parity, overrun, framing, and break detection
D Two wake-up multiprocessor modes: Idle-line and address bit
D Half or full-duplex operation
D Double-buffered receiver and transmitter operations
D Transmitter and receiver operations can be accomplished through either interrupt-driven or
polled-algorithms with status flags:
–
Transmitter: TXRDY flag (transmitter buffer register is ready to receive another character) and TX
EMPTY flag (Transmitter shift register is empty)
–
Receiver: RXRDY flag (receive buffer register ready to receive another character), BRKDT flag (break
condition occurred), and RX ERROR monitoring four interrupt conditions
–
Separate enable bits for transmitter and receiver interrupts
–
NRZ (non return-to-zero) format
D Eleven SCI1 module control registers, located in control register frame beginning at address P050h



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