TMS370 datasheet(33/66 Pages) TI

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TMS370Cx4x

8-BIT MICROCONTROLLER

SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

serial communications interface 1 (SCI1) (continued)

Table 15 lists the SCI1 module control registers.

Table 15. SCI1 Module Control Register Memory Map

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

P050

STOP BITS

EVEN/ODD

PARITY

ENABLE

ASYNC/

ISOSYNC

ADDRESS/

IDLE WUP

SCI CHAR2

SCI CHAR1

SCI CHAR0

SCICCR

P051

—

SCI SW

RESET

CLOCK

TXWAKE

SLEEP

TXENA

RXENA

SCICTL

P052

BAUDF

(MSB)

BAUDE

BAUDD

BAUDC

BAUDB

BAUDA

BAUD9

BAUD8

BAUD MSB

P053

BAUD7

BAUD6

BAUD5

BAUD4

BAUD3

BAUD2

BAUD1

BAUD0

(LSB)

BAUD LSB

P054

TXRDY

TX EMPTY

—

SCI TX

INT ENA

TXCTL

P055

ERROR

RXRDY

BRKDT

RXWAKE

SCI RX

INT ENA

RXCTL

P056

Reserved

P057

RXDT7

RXDT6

RXDT5

RXDT4

RXDT3

RXDT2

RXDT1

RXDT0

RXBUF

P058

RESERVED

P059

TXDT7

TXDT6

TXDT5

TXDT4

TXDT3

TXDT2

TXDT1

TXDT0

TXBUF

P05A

P05B

P05C

Reserved

P05D

—

SCICLK

DATA IN

SCICLK

DATA OUT

SCICLK

FUNCTION

SCICLK

DATA DIR

SCIPC1

P05E

SCITXD

DATA IN

SCITXD

DATA OUT

SCITXD

FUNCTION

SCITXD

DATA DIR

SCIRXD

DATA IN

SCIRXD

DATA OUT

SCIRXD

FUNCTION

SCIRXD

DATA DIR

SCIPC2

P05F

SCI STEST

SCITX

PRIORITY

SCIRX

PRIORITY

SCI

ESPEN

—

SCIPRI

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