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TMS370 Datasheet(PDF) 25 Page - Texas Instruments |
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TMS370 Datasheet(HTML) 25 Page - Texas Instruments |
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25 / 66 page  TMS370Cx4x 8-BIT MICROCONTROLLER SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997 25 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 timer 1 module (continued) D Hard watchdog configuration (see Figure 9) for mask-ROM devices only: – Eight different WD overflow rates ranging from 26.2 ms to 3.35 s at 5-MHz SYSCLK – A WD reset key (WDRST) register is used to clear the watchdog counter (WDCNTR) when a correct value is written. – Generates a system reset if an incorrect value is written to the WDRST or if the counter overflows – A WD overflow flag (WD OVRFL INT FLAG) bit that indicates whether the WD timer initiated a system reset – Automatic activation of the WD timer upon power-up reset – INT1 is enabled as a nonmaskable interrupt during low power modes. 16-Bit Watchdog Counter Reset Prescaler Clock Watchdog Reset Key WD OVRFL TAP SEL System Reset T1CTL1.7 WDRST.7-0 WDCNTR.15-0 T1CTL2.5 WD OVRFL INT FLAG Figure 9. Hard Watchdog |
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