TMS370 datasheet(13/66 Pages) TI

13 / 66 page

TMS370Cx4x

8-BIT MICROCONTROLLER

SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

interrupts

The TMS370 family software-programmable interrupt structure supports flexible on-chip and external interrupt

configurations to meet real-time interrupt-driven application requirements. The hardware interrupt structure

incorporates two priority levels as shown in Figure 4. Interrupt level 1 has a higher priority than interrupt

level 2. The two priority levels can be independently enabled by the global-interrupt enable bits (IE1 and IE2)

of the status register.

TIMER 2A

CPU

NMI

Logic

Enable

IE1

IE2

Level 1 INT

Level 2 INT

T2A PRI

Priority

Overflow

Compare1

Ext Edge

Compare2

Input Capture 1

Input Capture 2

EXT INT 3

INT3 PRI

INT 3

STATUS REG

EXT INT1

INT1 PRI

INT1

EXT INT 2

INT2 PRI

INT 2

AD INT

AD PRI

A/D

TIMER 1

T1 PRI

Overflow

Compare1

Ext Edge

Compare2

Input Capture 1

Watchdog

SCI INT

BRKDT

RXRDY

TXRDY

TXPRI

RXPRI

Figure 4. Interrupt Control

Each system interrupt is configured independently on either the high- or low-priority chain by the application

program during system initialization. Within each interrupt chain, the interrupt priority is fixed by the position of

the system interrupt. However, since each system interrupt is configured selectively on either the high- or

low-priority interrupt chain, the application program can elevate any system interrupt to the highest priority.

Arbitration between the two priority levels is performed within the CPU. Arbitration within each of the priority

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