TMS370 datasheet(14/66 Pages) TI

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TMS370Cx4x

8-BIT MICROCONTROLLER

SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

interrupts (continued)

chains is performed within the peripheral modules to support interrupt expansion to future modules. Pending

interrupts are serviced upon completion of current instruction execution, depending on their interrupt mask and

priority conditions.

The TMS370Cx4x has eight hardware system interrupts (plus RESET) as shown in Table 7. Each system

interrupt has a dedicated interrupt vector located in program memory through which control is passed to the

interrupt service routines. A system interrupt can have multiple interrupt sources (e.g., SCI RXNT has two

interrupt sources). All of the interrupt sources are individually maskable by local interrupt-enable control bits in

the associated peripheral file. Each interrupt source FLAG bit is individually readable for software polling or for

determining which interrupt source generated the associated system interrupt.

Five of the system interrupts are generated by on-chip peripheral functions, and three external interrupts are

supported. Software configuration of the external interrupts is performed through the INT1, INT2, and INT3

control registers in peripheral file frame 1. Each external interrupt is individually software-configurable for input

polarity (rising or falling) for ease of system interface. External interrupt INT1 is software-configurable as either

a maskable or non-maskable interrupt. When INT1 is configured as non-maskable, it cannot be masked by the

individual- or global-enable mask bits. The INT1 NMI bit is protected during non-privileged operation and,

therefore, should be configured during the initialization sequence following reset. To maximize pin flexibility,

external interrupts INT2 and INT3 can be software-configured as general-purpose input/output pins if the

interrupt function is not required (INT1 can be configured similarly as an input pin).

Table 7. Hardware System Interrupts

INTERRUPT SOURCE

INTERRUPT FLAG

SYSTEM

INTERRUPT

VECTOR

ADDRESS

PRIORITY†

External RESET

Watchdog Overflow

Oscillator Fault Detect

COLD START

WD OVRFL INT FLAG

OSC FLT FLAG

RESET‡

7FFEh, 7FFFh

External INT1

INT1 FLAG

INT1‡

7FFCh, 7FFDh

External INT2

INT2 FLAG

INT2‡

7FFAh, 7FFBh

External INT3

INT3 FLAG

INT3†

7FF8h, 7FF9h

Timer 1 Overflow

Timer 1 Compare 1

Timer 1 Compare 2

Timer 1 External Edge

Timer 1 Input Capture

Watchdog Overflow

T1 OVRFL INT FLAG

T1C1 INT FLAG

T1C2 INT FLAG

T1EDGE INT FLAG

T1IC INT FLAG

WD OVRFL INT FLAG

T1INT§

7FF4h, 7FF5h

SCI RX Data Register Full

SCI RX Break Detect

RXRDY FLAG

BRKDT FLAG

RXINT‡

7FF2h, 7FF3h

SCI TX Data Register Empty

TXRDY FLAG

TXINT

7FF0h, 7FF1h

Timer 2A Overflow

Timer 2A Compare 1

Timer 2A Compare 2

Timer 2A External Edge

Timer 2A Input Capture 1

Timer 2A Input Capture 2

T2A OVRFL INT FLAG

T2AC1 INT FLAG

T2AC2 INT FLAG

T2AEDGE INT FLAG

T2AIC1 INT FLAG

T2AIC2 INT FLAG

T2AINT

7FEEh, 7FEFh

A-D Conversion Complete

AD INT FLAG

ADINT

7FECh, 7FEDh

† Relative priority within an interrupt level.

‡ Releases microcontroller from STANDBY and HALT low-power modes.

§ Releases microcontroller from STANDBY low-power mode.

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