TPS65721 datasheet(33/50 Pages) TI

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TPS65720

TPS65721

www.ti.com

SLVS979 – OCTOBER 2009

CHGCONFIG2 Register Address: 04h (read/write)

CHGCONFIG2

Bit name and function

SFTY_TMR1 0

SFTY_TMR

PRE_TMR

NTC

V_DPPM

VBAT_COMP_EN

Default

Default value loaded

UVLO/R

by:

Read/write

R/W

Bit 7..6

SFTY_TMR1..SFTY_TMR0 (charge safety timer value):

00 = 4h

01 = 5h

10 = 6h

11 = 8h

Bit 5

PRE_TMR (pre-charge timer value):

0 = 30min

1 = 60min

Bit 3

NTC (sensor resistance):

0 = 100k NTC (I=7.5uA)

1 = 10k NTC (I=75uA)

Bit 2

V_DPPM (dynamic power path threshold):

0 = VBAT+100mV

1 = 4.3V

Bit 1

VBAT_COMP_EN (battery voltage comparator enable):

0 = battery voltage comparator for Li-primary cells disabled; VBAT_COMP interrupt disabled

1 = battery voltage comparator for Li-primary cells enabled

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