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TPS65721 Datasheet(PDF) 5 Page - Texas Instruments |
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TPS65721 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 50 page  TPS65720 TPS65721 www.ti.com SLVS979 – OCTOBER 2009 ELECTRICAL CHARACTERISTICS (continued) VSYS = 3.6V, VDCDC1 = 2.05V, PFM mode, L = 3.3μH, COUTDCDC1 = 4.7μF, VINLDO1=2.05V, VLDO1=1.85V, TA = –40°C to 85°C typical values apply in a temperature range of 10°C to 35°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DCDC1 disabled; the discharge function can be disabled as an RDIS Internal discharge resistor at L 300 400 Ω EEPROM option THERMAL PROTECTION FOR DCDC1 AND LDO1 TSD Thermal shutdown Increasing junction temperature 150 °C Thermal shutdown hysteresis Decreasing junction temperature 30 °C VLDO1 LOW DROPOUT REGULATOR VINLDO Input voltage range for LDO1 1.8 5.6 V VLDO1 LDO1 output voltage range 0.8 3.3 V VLDO1 LDO1 output voltage Default output voltage for TPS65720 only 1.85 V VFB_LDO1 Feedback voltage Externally adjustable version only: TPS65721 0.8 V IFB_LDO1 FB pin input current 0.1 μA IO Output current for LDO1 200 mA ISC LDO1 short circuit current limit VLDO1 = GND; VinLDO1=2.05V 350 500 mA Dropout voltage at LDO1, YFF package IO = 200 mA, VINLDO = 2.05 V 180 mV Dropout voltage at LDO1, RSN package IO = 200 mA, VINLDO = 2.05 V 120 mV Output voltage accuracy for LDO1 IO = 200 mA –1.5% 2.5% Line regulation for LDO1 VINLDO1 = VLDO1 + 0.5V (min. 1.8V) to 5.6 V (VSYS), IO = 50 mA –1% 1% Load regulation for LDO1 IO = 0 mA to 200 mA for LDO1 –1% 2% PGOOD debounce time Internal PGOOD comparator at VOUTLDO1 is debounced by 80 μs Internal soft-start when LDO is enabled; tRamp VOUT Ramp time 250 μs Time to ramp from 5% to 95% of VOUT LDO disabled, discharge function per default disabled in RDIS Internal discharge resistor at VLDO1 250 400 Ω register BATTERY VOLTAGE COMPARATOR Battery voltage comparator threshold voltage Depending on Bits <VBAT0>, <VBAT1>; falling voltage –3% 3% V Battery voltage comparator threshold voltage Rising voltage 200 mV hysteresis POWER PATH VUVLO Undervoltage lockout VAC: 0V → 4V 3.2 3.3 3.45 V VHYS-UVLO Hysteresis on UVLO VAC: 4V → 0V 200 300 mV (Input power detected if VIN > VBAT + VIN-DT) VBAT = 3.6V, VIN-DT Input power detection threshold 40 80 140 mV VIN: 3.5V → 4V VHYS-INDT Hysteresis on VIN-DT VBAT = 3.6 V, VIN: 4V → 3.5V 20 mV Time measured from VIN: 0V → 5V 1μs tDGL(PGOOD) Deglitch time, input power detected status 2 ms rise-time to PGOOD = LO VOVP Input over-voltage protection threshold VAC: 5 V → 7 V 6.4 6.6 6.8 V VHYS-OVP Hysteresis on OVP VAC: 11V → 5V 105 mV tBLK(OVP) Input over-voltage blanking time 50 μs Time measured from VAC: 11V → 5V 1μs tREC(OVP) Input over-voltage recovery time 2 ms fall-time to <CH_PGOOD>=0 ISYS = 0.3A, VAC = 4.35V, VBAT =4.2V; YFF package 170 285 mV AC pin to SYS pin dropout voltage VDO(AC-SYS) VAC – VSYS ISYS = 0.3A, VAC = 4.35V, VBAT =4.2V; RSN package 210 325 mV ISYS = 0.2A, VAC = 0V, VBAT > 3V; YFF package 80 mV Battery to SYS pin dropout voltage VDO(BAT-SYS) VBAT – VSYS ISYS = 0.2A, VAC = 0V, VBAT > 3V; RSN package 120 mV 00: VAC > VSYS + VDO(AC-SYS), VBAT < 3.3V –5% 3.4 5% VBAT + 00: VAC > VSYS + VDO(AC-SYS), VBAT >/= 3.3V –5% 5% 200mV SYS pin voltage regulation selectable register VSYS(REG) V <CHGCONFIG0> Bits <VSYS1>; <VSYS0> 01: VAC > VSYS + VDO(AC-SYS) –5% 4.4 5% 10: VAC > VSYS + VDO(AC-SYS) –5% 5.0 5% 11: VAC > VSYS + VDO(AC-SYS) –5% 5.5 5% Bit <AC input current1, AC input current0> = 00 90 95 100 mA IAC-MAX Maximum Input Current Register <CHCONFIG0> Bit < AC input current1, AC input current0> = 01 or 10 450 475 500 mA Input voltage threshold when input current is Input current is reduced if voltage at AC falls below VAC-LOW VAC-LOW 4.35 4.5 4.65 V reduced to keep the AC voltage above 4.5V Output voltage threshold when charging current is VO(REG) Bit <V_DPPM> = 1 V reduced –100mV VDPM Register <CHCONFIG2> Bit <V_DPPM> = 0 4.3 V Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): TPS65720 TPS65721 |
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