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TPS65721 Datasheet(PDF) 29 Page - Texas Instruments |
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TPS65721 Datasheet(HTML) 29 Page - Texas Instruments |
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29 / 50 page ![]() TPS65720 TPS65721 www.ti.com SLVS979 – OCTOBER 2009 MIN MAX UNIT fMAX Clock frequency 400 kHz twH(HIGH) Clock high time 600 ns twL(LOW) Clock low time 1300 ns tR DATA and CLK rise time 300 ns tF DATA and CLK fall time 300 ns th(STA) Hold time (repeated) START condition (after this period the first clock pulse is generated) 600 ns th(DATA) Setup time for repeated START condition 600 ns th(DATA) Data input hold time 0 ns tsu(DATA) Data input setup time 100 ns tsu(STO) STOP condition setup time 600 ns t(BUF) Bus free time 1300 ns All registers are set to their default value by one of the following events: • Voltage at the SYS pin is below the undervoltage lockout voltage (UVLO) • RESET is active; RESET output is pulled LOW and goes high with a 100ms delay Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 29 Product Folder Link(s): TPS65720 TPS65721 |
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