TPS65721 datasheet(17/50 Pages) TI

17 / 50 page

100

0.01

0.1

I -OutputCurrent- A

0.001

0.0001

0.00001

V =3V

V =3.6V

V =4.2V

V =5V

V =2.5V

460

465

470

475

480

485

490

495

500

505

4000

8000

12000

16000

20000

24000

ISET

=-40°C

=25°C

=85°C

TPS65720

TPS65721

www.ti.com

SLVS979 – OCTOBER 2009

Kset

Efficiency vs output current

for the complete system;

Riset

LDO1 powered by DCDC1 with VDCDC1=2.05V; VLDO1= 1.85V

Figure 21. ICH_SCL[1,0]=11

Figure 22.

DETAILED DESCRIPTION

BATTERY CHARGER AND POWER PATH

The TPS65720 integrates a Li-Ion linear charger and system power path management targeted at space-limited

portable applications. The TPS65720 powers the system while simultaneously and independently charging the

battery. This feature reduces the number of charge and discharge cycles on the battery, allows for proper charge

termination and enables the system to run with a defective or absent battery pack. It also allows instant system

turn-on even with a totally discharged battery. The input power source for charging the battery and running the

system can be an AC adapter or an USB port. The power-path management feature automatically reduces the

charging current if the system load increases. The power-path architecture also permits the battery to

supplement the system current requirements when the adapter cannot deliver the peak system currents.

POWER DOWN

The charger remains in power-down mode when the input voltage at the AC pin is below the under-voltage

lockout threshold (UVLO). During the power-down mode, the host commands through the I2C interface are

ignored. The Q1 FET connected between AC and SYS pins is off. The Q2 FET that connects BAT to SYS is ON.

(If <SYSOFF>=1, Q2 is off). During power-down mode, the VOUT(SC2) circuitry is active and monitors for

overload conditions on SYS.

SLEEP MODE

The charger enters sleep mode when VAC is greater than UVLO, but below VBAT + VIN(DT). In sleep mode, the

host commands are ignored. The Q1 FET connected between AC and SYS pins is off. The Q2 FET that

connects BAT to SYS is ON. (If <SYSOFF>=1, Q2 is off). During sleep mode, the VOUT(SC2) circuitry is active and

monitors for overload conditions on SYS.

STANDBY MODE

When VAC is greater than UVLO and VIN is greater than VBAT + VIN(DT), the device is in standby mode.

<CH_PGOOD> =1 to indicate the valid power status and the host commands are read. The device enters

standby mode whenever <AC input current1, AC input current0> = (0,0) or if an input overvoltage condition

occurs. In standby mode, Q1 is OFF and Q2 is ON. (If <SYSOFF>=1, Q2 is off). During standby mode, the

VOUT(SC2) circuitry is active and monitors for overload conditions on SYS.

Submit Documentation Feedback

Product Folder Link(s): TPS65720 TPS65721

TPS65721 Datasheet(PDF) 17 Page - Texas Instruments

TPS65721 Datasheet(HTML) 17 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Datasheet Download

Link URL