MAC7200 datasheet(267/976 Pages) FREESCALE

267 / 976 page

Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

189

11.11.5.5 Timing Diagram

Figure 11-51. A7S Nexus3 DMA clock relationships

The A7S Nexus3 Read/Write access timing meets the timing requirements for the AHB. The Nexus

module uses the processor clock gated with an AHB clock enable for all DMA transfers. This clock will

correspond to the rising edge of the actual AHB clock. The timing diagram in Figure 11-51 above shows

the relationship between the processor clock (CLK), the AHB clock (HCLK) and the AHB clock enable

(HCLKEN) for DMA writes and reads. Using this clocking method for Nexus read/write access eliminates

the need for a separate asynchronous clock input into the A7S Nexus3 module.

11.11.6 System Status

11.11.6.1 Debug Status Messages

Debug Status Messages report low power mode and debug status. Entering/exiting Debug Mode as well

as entering a Low Power Mode will trigger a Debug Status Message. Debug status information is sent out

in the following format:

(5 bits)

(4 bits)

(6 bits)

Error Code (00011)

Src. Proc.

TCODE (001000)

Fixed length = 15 bits

Figure 11-50. Error Message Format

(8 bits)

(4 bits)

(6 bits)

DS[31:24]

SRC

TCODE (000000)

Fixed length = 18 bits

Figure 11-52. Debug Status Message Format

CLK

HCLKEN

HCLK

AHB outputs (from Nexus)

AHB inputs (@ Nexus reg.)

MAC7200 Datasheet(PDF) 267 Page - Freescale Semiconductor, Inc