MAC7200 datasheet(15/976 Pages) FREESCALE

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MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

13.2.2.1

Processor Core Type (PCT) .....................................................................................245

13.2.2.2

Revision (REV) .......................................................................................................246

13.2.2.3

AXBS Master Configuration (AMC) ......................................................................246

13.2.2.4

AXBS Slave Configuration (ASC)..........................................................................247

13.2.2.5

IPS Module Configuration (IMC) ...........................................................................247

13.2.2.6

Miscellaneous Reset Status Register (MRSR) ........................................................248

13.2.2.7

Miscellaneous Wakeup Control Register (MWCR) ................................................249

13.2.2.8

Miscellaneous Software Watchdog Timer Control Register (MSWTCR) ..............250

13.2.2.9

Miscellaneous Software Watchdog Timer Service Register (MSWTSR) ...............252

13.2.2.10

Miscellaneous Interrupt Register (MIR)..................................................................253

13.2.2.11

AXBS Address Map Register (AAMR) ..................................................................254

13.2.2.12

Miscellaneous User-Defined Control Register (MUDCR)......................................255

13.2.2.13

NMI Control Register (NMICR) .............................................................................256

13.2.2.14

Peripheral Power Management Registers (PPMR)..................................................257

13.2.2.14.1

Peripheral Power Management Set Register (PPMRS).......................................257

13.2.2.14.2

Peripheral Power Management Clear Register (PPMRC)...................................258

13.2.2.14.3

Peripheral Power Management Set Register 1 (PPMRS1)..................................259

13.2.2.14.4

Peripheral Power Management Clear Register 1 (PPMRC1)..............................259

13.2.2.14.5

Peripheral Power Management Register (PPMR{H,L}).....................................260

13.2.2.14.6

Peripheral Power Management Register 1 (PPMR1{H,L})................................261

13.2.2.15

ECC Registers..........................................................................................................263

13.2.2.15.1

ECC Configuration Register (ECR) ....................................................................263

13.2.2.15.2

ECC Status Register (ESR) .................................................................................265

13.2.2.15.3

ECC Error Generation Register (EEGR).............................................................266

13.2.2.15.4

Flash ECC Address Register (FEAR) .................................................................269

13.2.2.15.5

Flash ECC Master Number Register (FEMR).....................................................270

13.2.2.15.6

Flash ECC Attributes Register (FEAT) ...............................................................271

13.2.2.15.7

Flash ECC Data Register (FEDR) .......................................................................272

13.2.2.15.8

RAM ECC Address Register (REAR).................................................................272

13.2.2.15.9

RAM ECC Syndrome Register (RESR) ..............................................................273

13.2.2.15.10

RAM ECC Master Number Register (REMR)....................................................274

13.2.2.15.11

RAM ECC Attributes Register (REAT) ..............................................................275

13.2.2.15.12

RAM ECC Data Register (REDR) ......................................................................276

13.2.2.16

Core Data Fault Recovery Registers........................................................................277

13.2.2.16.1

Core Fault Address Register (CFADR) ...............................................................277

13.2.2.16.2

Core Fault Location/Interrupt Enable Register (CFLOC1) .................................278

13.2.2.16.3

Core Fault Location Register (CFLOC) ..............................................................279

13.2.2.16.4

Core Fault Attributes Register (CFATR) .............................................................279

13.2.2.16.5

Core Fault Data Register (CFDTR).....................................................................280

13.3

MCM as Implemented on MAC7200 ..............................................................................281

13.3.1

MCM Introduction.......................................................................................................281

13.3.2

MCM Features .............................................................................................................282

13.3.2.1

Processor Core Type (PCT) .....................................................................................282

13.3.2.2

Revision ID (REV) ..................................................................................................283

13.3.2.3

AXBS Master/Slave Configuration .........................................................................283

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