MAC7200 datasheet(18/976 Pages) FREESCALE

18 / 976 page

MAC7200 Microcontroller Family Reference Manual, Rev. 2

xviii

Freescale Semiconductor

16.2.1

8/16/32--bit accesses....................................................................................................325

16.3

External Signal Description .............................................................................................329

16.4

Memory Map/Register Definition ...................................................................................329

16.4.1

Overview......................................................................................................................330

16.4.2

Control Registers .........................................................................................................330

16.4.3

Register Descriptions...................................................................................................331

16.4.3.1

Master Privilege Registers (MPROT) .....................................................................331

16.4.3.2

Peripheral Access Control Registers (PACR)..........................................................332

16.4.3.3

Off-Platform Peripheral Access Control Registers (OPACRs) ...............................333

16.5

Functional Description.....................................................................................................333

16.5.1

AIPS Scalability...........................................................................................................333

16.5.1.1

Peripheral Presence..................................................................................................333

16.5.1.2

Registers ..................................................................................................................334

16.5.2

Access Protections .......................................................................................................334

16.5.3

Access Support ............................................................................................................334

16.5.4

Read Cycles .................................................................................................................334

16.5.5

Write Cycles.................................................................................................................334

16.5.6

Aborted Cycles ............................................................................................................334

16.6

Initialization/Application Information .............................................................................335

16.7

AIPS Bus Aborts..............................................................................................................335

16.7.1

IPI Register Interface ...................................................................................................335

16.7.2

IPI Bridge Interface .....................................................................................................335

16.8

AIPS Differences from MAC71xx ..................................................................................336

Chapter 17

External Bus Interface (FlexBus)

17.1

Introduction......................................................................................................................339

17.1.1

Block Diagram.............................................................................................................340

17.1.2

Features........................................................................................................................340

17.1.3

FlexBus Implementation..............................................................................................341

17.1.4

FlexBus Memory Map Relocation...............................................................................341

17.2

External Signals ...............................................................................................................341

17.2.1

Chip-Select (CS[2:0]) ..................................................................................................342

17.2.2

Address Bus (ADDR[21:0]) ........................................................................................342

17.2.3

Data Bus (DATA[15:0])...............................................................................................342

17.2.4

Read/Write (R/W) ........................................................................................................342

17.2.5

Transfer Burst (TBST) .................................................................................................342

17.2.6

Byte Write Enable/Byte Select (BWE[1:0]) ...............................................................342

17.2.7

Output Enable (OE) .....................................................................................................342

17.2.8

Transfer Acknowledge (TA) ........................................................................................343

17.3

Chip-Select Operation......................................................................................................343

17.3.1

General Chip-Select Operation....................................................................................343

17.3.1.1

8-bit and 16-bit Port Sizing......................................................................................343

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