MAC7200 datasheet(47/976 Pages) FREESCALE

47 / 976 page

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

xlvii

29-10

I2C Bus Data I/O Register (IBDR) ......................................................................................559

29-11

I2C Bus Interrupt Config Register (IBIC)............................................................................560

29-12

I2C Bus Transmission Signals .............................................................................................561

29-13

Start and Stop conditions .....................................................................................................561

29-14

I2C Bus Clock Synchronization ...........................................................................................563

29-15

Flow-Chart of Typical I2C Interrupt Routine ......................................................................568

29-16

Flow-Chart of DMA Mode Master Transmit.......................................................................570

29-17

Flow-Chart of DMA Mode Master Receive ........................................................................571

30-1

DSPI Block Diagram ...........................................................................................................579

30-2

DSPI with Queues and DMA...............................................................................................580

30-3

DSPI Module Configuration Register (DSPI_MCR) ..........................................................584

30-4

DSPI Transfer Count Register (DSPI_TCR) .......................................................................586

30-5

DSPI Clock and Transfer Attributes Register 0–7 (DSPI_CTAR0–DSPI_CTAR7) ..........587

30-6

DSPI Status Register (DSPI_SR).........................................................................................593

30-7

DSPI DMA/Interrupt Request Select and Enable Register (DSPI_RSER) .........................595

30-8

DSPI PUSH TX FIFO Register (DSPI_PUSHR) ................................................................596

30-9

DSPI POP RX FIFO Register (DSPI_POPR)......................................................................598

30-10

DSPI Transmit FIFO Register 0–3 (DSPI_TXFR0–DSPI_TXFR3) ...................................598

30-11

DSPI Receive FIFO Registers 0–3 (DSPI_RXFR0–DSPI_RXFR3 ....................................599

30-12

SPI Serial Protocol Overview ..............................................................................................600

30-13

DSPI Start and Stop State Diagram .....................................................................................602

30-14

Communications Clock Prescalers and Scalers ...................................................................605

30-15

Peripheral Chip Select Strobe Timing .................................................................................607

30-16

DSPI Transfer Timing Diagram (MTFE=0, CPHA=0, FMSZ=8) ......................................609

30-17

DSPI Transfer Timing Diagram (MTFE=0, CPHA=1, FMSZ=8) ......................................610

30-18

DSPI Modified Transfer Format (MTFE=1, CPHA=0, Fsck = Fsys/4) ..............................611

30-19

DSPI Modified Transfer Format (MTFE=1, CPHA=1, Fsck = Fsys/4) ..............................612

30-20

Example of Non-Continuous Format (CPHA=1, CONT=0) ...............................................613

30-21

Example of Continuous Transfer (CPHA=1, CONT=1) ....................................................613

30-22

Continuous SCK Timing Diagram (CONT=0)....................................................................614

30-23

Continuous SCK Timing Diagram (CONT=1)....................................................................615

30-24

Example of a DSPI in an SoC with a Power Management Block .......................................617

30-25

TX FIFO Pointers and Counter............................................................................................622

31-1

eSCI Block Diagram ............................................................................................................626

31-2

SCI Baud Rate Register High (SCIBDH) ............................................................................634

31-3

SCI Baud Rate Register Low (SCIBDL) .............................................................................635

31-4

SCI Control Register 1 (SCICR1)........................................................................................635

31-5

SCI Control Register 2 (SCICR2)........................................................................................637

31-6

SCI Control Register 3 (SCICR3)........................................................................................638

31-7

SCI Control Register 4 (SCICR4)........................................................................................639

31-8

SCI Data Register High (SCIDRH) .....................................................................................639

31-9

SCI Data Register Low (SCIDRL) ......................................................................................640

31-10

SCI Status Register 1 (SCISR1) ..........................................................................................641

31-11

SCI Status Register 2 (SCISR2) ..........................................................................................642

31-12

LIN Status Register 1 (LINSTAT1) ....................................................................................642

MAC7200 Datasheet(PDF) 47 Page - Freescale Semiconductor, Inc

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