MAC7200 datasheet(82/976 Pages) FREESCALE

82 / 976 page

Features

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

— Programmable I/O modes.

— External transceiver assumed.

•

Enhanced Modular I/O Subsystem features (eMIOS)

— 8 unified channels (MAC72x2) / 16 unified channels (MAC72x1), with every channel

able to provide all timer functions and modes.

— All channels can be enabled for eDMA service.

— Channels can be individually disabled to assist with power saving.

— Two or three 16-bit counter buses (A and B, or A, B, and C) for sharing time base around the

module.

— One global prescaler and an individual prescaler available for each channel.

— Modulus counter mode on all channels.

— Single action input capture or output compare modes on all channels.

— Input pulse width and period measurement modes on all channels.

— Double action output compare mode on all channels.

— Output pulse width and frequency modulation modes on all channels.

— Output pulse width modulation modes on all channels.

— Center aligned output pulse width modulation with dead time insertion modes on all channels.

— Pulse or edge accumulation and counting modes on all channels.

— Windowed programmable time accumulation mode on all channels.

— Quadrature decode modes on all channels.

— General purpose I/O available on unused eMIOS pins.

— Center-aligned PWM with dead-time insertion

•

Three Serial Peripheral Interface features (DSPI)

— Full Duplex, Synchronous Transfers.

— Master or Slave Operation.

— Programmable Master Bit Rates.

— Programmable Clock Polarity and Phase.

— End-of-Transmission Interrupt Flag.

— Programmable transfer Baud rate.

— Programmable data frames from 4-bits to 16-bits.

— Up to 6 chip select lines enable 64 external devices to be selected using external multiplexing

from a single DSPI.

— 8 Clock and Transfer Attributes registers.

— Chip Select Strobe available as alternate function on one of the Chip Select pins for

de-glitching.

— Two dedicated DMA request lines on each peripheral for receive and transmit data.

— FIFO for buffering up to 4 transfers on the transmit and receive side.

— Queueing operation possible through use of the DMA controllers channels.

MAC7200 Datasheet(PDF) 82 Page - Freescale Semiconductor, Inc

MAC7200 Datasheet(HTML) 82 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL