MAC7200 datasheet(51/976 Pages) FREESCALE

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MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

34-12

Global Interrupt Status Register (GLBLINT)......................................................................825

34-13

PIM Configuration Register (PICONFIG)...........................................................................825

34-14

Pin Configuration Register (CONFIG_TDI) .......................................................................826

34-15

Pin Configuration Register (CONFIG_TDO)......................................................................827

34-16

Pin Configuration Register (CONFIG_TMS)......................................................................828

34-17

Pin Configuration Register (CONFIG_TCK) ......................................................................829

34-18

Pin Configuration Register (CONFIG_RESET)..................................................................830

34-19

Pad in Peripheral Mode (including pad PD2) ......................................................................833

34-20

Pad in GPI Mode (including pad PD2) ................................................................................836

34-21

External Interrupt Timing Requirements .............................................................................838

34-22

Pad in GPO Mode (except pad PD2) ...................................................................................839

34-23

Pad PD2 in GPO Mode ........................................................................................................840

34-24

I/O Pad Control (Overview).................................................................................................841

34-25

I/O Pad Control (Detailed View) .........................................................................................842

34-26

PIM Peripheral Muxing .......................................................................................................843

34-27

I/O Pad Control Cell Architecture (in PIM core).................................................................844

A-1

Basic PLL Functional Diagram ...........................................................................................871

A-2

General Purpose Input Timing Specifications .....................................................................874

A-3

General Purpose Output Timing Specifications ..................................................................875

A-4

Nexus Output Timing Specifications...................................................................................876

A-5

JTAG Port Timing Specifications........................................................................................877

A-6

SPI Master Timing (CPHA = 0) ..........................................................................................878

A-7

SPI Master Timing (CPHA = 1) ..........................................................................................879

A-8

SPI Slave Timing (CPHA = 0).............................................................................................880

A-9

SPI Slave Timing (CPHA = 1).............................................................................................880

A-10

External Bus Input Timing Specifications ...........................................................................881

A-11

Read/Write (Internally Terminated) Bus Timing ................................................................883

A-12

Read Bus Cycle Terminated by TA .....................................................................................884

A-13

ATD Accuracy Definitions ..................................................................................................888

A-14

ATD External Trigger Timing Diagram ..............................................................................890

A-15

I2C Input/Output Timings ....................................................................................................891

MAC7200 Datasheet(PDF) 51 Page - Freescale Semiconductor, Inc

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