MAC7200 datasheet(50/976 Pages) FREESCALE

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MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

33-4

ATD Prescaler Register (ATDPRE) ....................................................................................749

33-5

ATD Operating Modes Register (ATDMODE) ..................................................................750

33-6

32ATD Calibration Register (ATDCAL) ............................................................................751

33-7

ATD Predischarge Time Select Register (ATDPTS) ..........................................................753

33-8

ATD Interrupt Register (ATDINT) .....................................................................................753

33-9

ATD Flag Register (ATDFLAG).........................................................................................754

33-10

ATD Command Word Register (ATDCW) .........................................................................756

33-11

RRCR for Right Justified Unsigned ....................................................................................758

33-12

RRCR for Right Justified Signed.........................................................................................759

33-13

RRCR for Left Justified Unsigned.......................................................................................759

33-14

RRCR for Left Justified Signed 8/10 Bit .............................................................................759

33-15

ATD Result Register (ATDRR)...........................................................................................761

33-16

ATD Command Queue / Result Register.............................................................................766

33-17

Flow Diagram for Command Processing.............................................................................768

33-18

Flow Diagram for Result Saving/Command Fetching.........................................................769

33-19

Command vs. Result Timing ...............................................................................................769

33-20

Various Conversion Phases..................................................................................................770

33-21

Predischarge Circuit.............................................................................................................773

33-22

Predischarge Timing ............................................................................................................773

33-23

Gain Error (Gain Too High) Compensated via GCC and OCC...........................................776

33-24

Gain Error (Gain Too High) Compensated via Warp ..........................................................777

33-25

Gain Error (Gain Too Low) Compensated via GCC ...........................................................778

33-26

Offset Error Compensated via OCC ....................................................................................779

33-27

Conversion Procedure for Example 1 ..................................................................................783

33-28

Conversion Procedure for Example 2 ..................................................................................785

33-29

Conversion Procedure for Example 3 ..................................................................................786

33-30

Conversion Procedure for Example 4 ..................................................................................787

33-31

ATD Edge-Based Trigger Example.....................................................................................787

33-32

Conversion Procedure for Example 4 ..................................................................................788

33-33

ATD Level-Based Minimum Trigger ..................................................................................788

33-34

Conversion Procedure for Example 6 ..................................................................................789

33-35

Conversion Procedure for Example 7 ..................................................................................790

33-36

Conversion Procedure for Example 8 (part 1) .....................................................................790

33-37

Conversion Procedure for Example 8 (part 2) .....................................................................791

34-1

Port Integration Module Block Diagram .............................................................................797

34-2

PIM Peripheral Muxing .......................................................................................................807

34-3

Pin Configuration Register (CONFIGxx, Port A, B, C, D, F, G) ........................................817

34-4

Pin Configuration Register (CONFIGxx, Port E) ................................................................819

34-5

Port Wide Interrupt Flag Register (PORTIFR)....................................................................820

34-6

Port Wide Data Register (PORTDATA, Port A, B, C, D, F, G) .........................................820

34-7

Port Wide Data Register (PORTDATA Port E) ..................................................................821

34-8

Port Wide Input Register (PORTIR, Port A, B, C, D, F, G)................................................822

34-9

Port Wide Input Register (PORTIR, Port E) .......................................................................823

34-10

Pin Data Register (PINDATAxx, Port A, B, C, D, F, G).....................................................823

34-11

Pin Data Register (PINDATAxx, Port E) ............................................................................824

MAC7200 Datasheet(PDF) 50 Page - Freescale Semiconductor, Inc

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