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MAC7200 Datasheet(PDF) 69 Page - Freescale Semiconductor, Inc |
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MAC7200 Datasheet(HTML) 69 Page - Freescale Semiconductor, Inc |
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69 / 976 page ![]() Terminology MAC7200 Microcontroller Family Reference Manual, Rev. 2 Freescale Semiconductor lxix FC Flash Core, contains all addressable non-volatile storage elements. This includes Low Address Space, Mid Address Space, High Address Space, and Shadow Space. Also known as Flash Array. Field Two or more register bits grouped together. Fill To add entries to a FIFO by software or hardware. Flash Array A non-volatile SuperFlash® memory array used to build the Program Flash blocks, which includes a Flash memory core with built-in high voltage generation and parametric features. Flash Logical Page 4096 bytes of contiguous Flash memory consisting of two interleaved Flash physical blocks representing the smallest section of the Flash memory that can be erased. Flash Logical Sector Section of contiguous Flash memory that can be protected from program, erase, and unauthorized access. Flash User Mode Flash module operations defined for User/Normal mode. Frame The data content of a serial transmission. Also referred to as DSPI Data. FSM Finite State Machine GPIO General purpose Input/Output H7Fb HiP7a Low Cost Flash EEPROM Module. Hard Reset Reset coming from external pin and/or following power-on. It resets everything. HAS High Address Space. If it exists, it contains 128k Byte subdivisions of the H7Fb array. Host Refers to the MCU or other bus master module IEEE-ISTO 5001 Consortium & standard for real-time embedded system design. World wide Web documentation at http://www.nexus5001.org/. IIB Internal Interface Bus input capture Sampling of a time base value upon the occurrence of an input signal transition. IPI Internal Peripheral Interface - a Freescale peripheral slave bus IPF Input Programmable Filter IPM Input Period Measurement IPS Intelligent Peripheral Subsystem bus interface JTAG Compliant Device complying to IEEE 1149.1 JTAG standard JTAG IR & DR Sequence JTAG Instruction Register (IR) scan to load an opcode value for selecting a development register. The selected development register is then accessed via a JTAG Data Register (DR) scan. LAS Low Address Space. 256KByte in size. Various configurations exist for Low Address Space. May also be 128KByte in size if total memory size is 128KByte (i.e. No MAS or HAS). LC Loop Control LIN Local Interconnect Network – A protocol for low-cost automobile networks LIN FSM LIN Finite State Machine – The control logic of the LIN hardware Table ii. Terminology (Continued) Terms Description |
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