MAC7200 datasheet(275/976 Pages) FREESCALE

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Overview of the MAC7200 Implementation

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

197

12.1.6.3.2

Error Signalling

The DMA module has the capability to report three types of errors, with each error detected and reported

on a channel-by-channel basis:

— Source bus error

— Destination bus error

— Configuration error

You must choose whether to implement error handling in an interrupt driven or polling method. For

interrupt driven error handling, perform the following steps:

1. For each channel desired, set the corresponding bit in the DMAEEIL register. Alternatively,

individual channels may also be configured by writing the corresponding DMASEEI or

DMACEEI registers to respectively set or clear a DMAEEIL bit. To enable interrupt driven error

handling for all channels, simply write $FF to the DMASEEI register.

2. When an interrupt occurs (Interrupt #0), read the DMAERRL register to determine all current

pending errors. Note that a channel may have an error pending even though its corresponding

Enable Error Interrupt (DMAEEIL) register bit was cleared. Also note that multiple channels may

have pending errors at the same time.

3. Detailed information about the last recorded channel error can be obtained by reading the DMAES

4. Once all errors have been detected (i.e.-Step #2), clear the errors by clearing the corresponding bits

in the DMAERRL register. To clear individual bits, you may also write to the DMACERR register.

If you want to clear all pending errors, simple write $FF to the DMACERR register.

To handles error in a polled fashion, following these steps:

1. For each channel desired, clear the corresponding bit in the DMAEEIL register. Alternatively,

individual channels may also be configured by writing the corresponding DMASEEI or

DMACEEI registers to respectively set or clear a DMAEEIL bit.

2. When desired, read the DMAERRL register to determine all current pending errors. Note that

multiple channels may have pending errors at the same time.

3. Detailed information about the last recorded channel error can be obtained by reading the DMAES

4. Once all errors have been detected (i.e.-Step #2), clear the errors by clearing the corresponding bits

in the DMAERRL register. To clear individual bits, you may also write to the DMACERR register.

If you want to clear all pending errors, simple write $FF to the DMACERR register.

NOTE

As evident from the above steps, it would be very difficult to use polling

driven error handling with peripheral paced channel activation (See below).

For this reason, it is recommended to use interrupt driven error handling in

most cases, and especially when not using explicit software activation of

channels.

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