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MAC7200 Datasheet(PDF) 292 Page - Freescale Semiconductor, Inc |
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MAC7200 Datasheet(HTML) 292 Page - Freescale Semiconductor, Inc |
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292 / 976 page ![]() The SPP DMA Controller Module (SPP_DMA2) MAC7200 Microcontroller Family Reference Manual, Rev. 2 214 Freescale Semiconductor bit is set, then the corresponding DMAERQ bit is cleared, disabling the DMA request; else if the d_req bit is cleared, the state of the DMAERQ bit is unaffected. 12.2.4.1.4 DMA Enable Error Interrupt (DMAEEIH, DMAEEIL) The DMAEEI{H,L} registers provide a bit map for the implemented channels {16,32,64} to enable the error interrupt signal for each channel. DMAEEIH supports channels 63-32, while DMAEEIL covers channels 31-00. The state of any given channel’s error interrupt enable is directly affected by writes to this register; it is also affected by writes to the DMASEEI and DMACEEI registers. The DMA{S,C}EEI registers are provided so that the error interrupt enable for a single channel can easily be modified without the need to perform a read-modify-write sequence to the DMAEEI{H,L} registers. Both the DMA error indicator and this error interrupt enable flag must be asserted before an error interrupt request for a given channel is asserted. See Figure 12-5 and Table 12-8 for the DMAEEI definition. Register address: DMA_Offset + 0x0010 (DMAEEIH), + 0x0014 (DMAEEIL) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0000000000000000 W Reset 0000000000000000 15 14 13 12 11 10 9876543210 R 0000000000000000 W Reset 0000000000000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0000000000000000 W Reset 0000000000000000 15 14 13 12 11 10 9876543210 R W Reset 0000000000000000 Figure 12-5. DMA Enable Error Interrupt (DMAEEIH, DMAEEIL) Registers |
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