DAC3282 datasheet(21/53 Pages) TI

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InstructionCycle

Data TransferCycle

tS(SDENB)

tS( SDIO) tH(SDIO)

tSCLK

tSCLKH

tSCLKL

SDENB

SCLK

SDIO

SDENB

SCLK

SDIO

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InstructionCycle

Data TransferCycle

td (Data)

SDENB

SCLK

SDIO

SDENB

SCLK

SDIOor

ALARM_SDO

ALARM_

SDO

Datan

Datan-1

3-pininterface

4-pininterface

DAC3282

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SLAS646A – DECEMBER 2009 – REVISED FEBRUARY 2010

Figure 32. Serial Interface Write Timing Diagram

Figure 33 shows the serial interface timing diagram for a DAC3282 read operation. SCLK is the serial interface

clock input to DAC3282. Serial data enable SDENB is an active low input to DAC3282. SDIO is serial data in

during the instruction cycle. In 3 pin configuration, SDIO is data out from DAC3282 during the data transfer

cycle(s), while ALARM_SDO is in a high-impedance state. In 4 pin configuration, ALARM_SDO is data out from

DAC3282 during the data transfer cycle(s). At the end of the data transfer, ALARM_SDO will output low on the

final falling edge of SCLK until the rising edge of SDENB when it will 3-state.

Figure 33. Serial Interface Read Timing Diagram

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