DAC3282 datasheet(23/53 Pages) TI

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DAC3282

www.ti.com

SLAS646A – DECEMBER 2009 – REVISED FEBRUARY 2010

Default

Address

Bit

Name

Function

Name

Value

CONFIG0

0x00

qmc_offset_ena

When asserted the DAC offset correction is enabled.

When asserted the FIFO is enabled. When the FIFO is bypassed

fifoin_ena

DACCCLKP/N and DATACLKP/N must be aligned to within t_align.

fifo_reset_ena

Allows the FRAME input to act as a FIFO write reset when asserted..

Allows the FRAME or OSTR signals to be used as a sync signal when

multi_sync_ena

asserted.

This selection is determined by multi_sync_sel in register CONFIG19.

When asserted the ALARM_SDO pin becomes an output. The

alarm_out_ena

functionality of this pin is controlled by the CONFIG6 alarm_mask

setting.

This bit changes the polarity of the ALARM signal. (0=negative logic,

alarm_pol

1=positive

1:0

mixer_func(1:0)

Controls the function of the mixer block.

Mode

mixer_func(1:0)

Normal

High Pass(Fs/2)

Fs/4

–Fs/4

Default

Address

Bit

Name

Function

Name

Value

CONFIG1

0x01

Unused

Reserved for factory use.

Unused

Reserved for factory use.

Unused

Reserved for factory use.

fir_ena

When asserted the chip does 2X interpolation of the data.

When asserted, the zero-IF sinc correction filter is enabled. This filter

fir4_ena

cannot be used unless fir_ena is asserted.

iotest_ena

When asserted enables the data pattern checker operation.

Unused

Reserved for factory use.

When asserted the inputs are expected to be in 2’s complement

twos

format. When de-asserted the input format is expected to be

offset-binary.

Default

Address

Bit

Name

Function

Name

Value

CONFIG2

0x02

Unused

Reserved for factory use.

Unused

Reserved for factory use.

Unused

Reserved for factory use.

Unused

Reserved for factory use.

3:0

output_delay(3:0)

Delays the output to the DACs from 0 to 15 DAC clock cycles.

0000

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