DAC3282 datasheet(30/53 Pages) TI

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DATACLKP /N

(DDR)

FRAMEP/N

D[7:0]P/N

SAMPLE 0

SAMPLE 1

t(FRAME)

[15:8]

[7:0]

[15:8]

[7:0]

[15:8]

[7:0]

[15:8]

[7:0]

Frame Align

FRAME

D[7:0]

FIFOIOutput

FIFOQOutput

ClockHandoff

InputSide

Clockedby DATACLK

OutputSide

ClockedbyFIFOOutClock

(DACCLK/InterpolationFactor)

FIFO:

2 x 16-bitswide

8-samplesdeep

Sample 0

I0[15:0], Q0[15:0]

Sample 2

I2[15:0], Q2[15:0]

Sample 3

I3[15:0], Q3[15:0]

Sample 4

I4[15:0], Q4[15:0]

Sample 5

I5[15:0], Q5[15:0]

Sample 6

I6[15:0], Q6[15:0]

Sample 7

I7[15:0], Q7[15:0]

Sample 1

I1[15:0], Q1[15:0]

Initial

Position

Initial

Position

32-bit

I-data, 16-bit

Q-data, 16-bit

16-bit

Data[15:8]

Data[7:0]

Twocycles, oneforI-dataandanother

forQ-data

8-bit

WritePointerReset

ReadPointerReset

DAC3282

SLAS646A – DECEMBER 2009 – REVISED FEBRUARY 2010

www.ti.com

FUNCTIONAL DESCRIPTION

DATA INTERFACE

The DAC3282 has a single 8-bit LVDS bus that accepts dual, 16-bit data input in byte-wide format. Data into the

DAC3282 is formatted according to the diagram shown in Figure 34 where index 0 is the data LSB and index 15

is the data MSB. The data is sampled by DATACLK, a double data rate (DDR) clock.

The FRAME signal is required to indicate the beginning of a frame. The frame signal can be either a pulse or a

periodic signal where the frame period corresponds to 8 samples. The pulse-width (t(FRAME)) needs to be at least

equal to 1/2f the DATACLK period. FRAME is sampled by a rising edge in DATACLK.

The setup and hold requirements listed in the specifications tables must be met to ensure proper sampling.

Figure 34. Byte-Wide Data Transmission Format

INPUT FIFO

The DAC3282 includes a 2-channel, 16-bits wide and 8-samples deep input FIFO which acts as an elastic buffer.

The purpose of the FIFO is to absorb any timing variations between the input data and the internal DAC data

rate clock such as the ones resulting from clock-to-data variations from the data source.

Figure 35 shows the block diagram of the FIFO.

Figure 35. DAC3282 FIFO Block Diagram

Data is written to the device 8-bits at a time on the rising and falling edges of DATACLK. In order to form a

complete 32-bit wide sample (16-bit I-data and 16-bit Q-data) two DATACLK periods are required as shown in

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