DAC3282 datasheet(32/53 Pages) TI

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DAC3282

SLAS646A – DECEMBER 2009 – REVISED FEBRUARY 2010

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Table 4. FIFO Operation Modes

CONFIG0 FIFO Bits

FIFO Mode

fifo_ena

fifo_reset_ena

multi_sync_ena

Enabled

Bypass

Enabled Mode

This is the recommended mode of operation for the DAC3282. In FIFO enabled mode, the FIFO is active and

can be reset continuously or only once during initialization. To reset only once, fifo_reset_ena must be set to 0

after initialization.

Bypass Mode

In FIFO bypass mode, the FIFO block is not used. As a result the input data is handed off from the DATACLK to

the DACCLK domain without any compensation. In this mode the relationship between DATACLK and DACCLK

(t_align) is critical and used as a synchronizing mechanism for the internal logic. Due to the t_align constraint it is

highly recommended that a clock synchronizer device such as Texas Instruments’ CDCM7005 or CDCE62005 is

used to provide both clock inputs. In bypass mode the pointers have no effect on the data path or handoff.

DATA PATTERN CHECKER

The DAC3282 incorporates a simple pattern checker test in order to determine errors in the data interface. The

test mode is enabled by asserting iotest_ena in register CONFIG1. In test mode the analog outputs are

deactivated regardless of the state of TXENABLE.

The data pattern key used for the test is 8 words long and is specified by the contents of iotest_pattern[0:7] in

registers CONFIG9 through CONFIG16. The data pattern key can be modified by changing the contents of these

registers.

The first word in the test frame is determined by a rising edge transition in FRAMEP/N. The test mode

determines if one or more words were received incorrectly by comparing the received data against the data

pattern key. The bits in iotest_results(7:0) in register CONFIG8 indicate which words were received incorrectly.

Furthermore, an error condition will trigger the alarm_from_iotest bit in register CONFIG7. Once set, the

alarm_from_iotest bit must be reset through the serial interface to allow further testing. Alternatively, the

64cnt_ena bit in register CONFIG3 can be enabled to reset the alarms automatically after 64 good samples

without the need for a SIF write to clear the alarm.

FIR FILTERS

The DAC3282 has two FIR filters, a 2x interpolation FIR (FIR0) and a non-interpolating FIR (FIR4) that

compensates for the sinc droop of the DAC on zero-IF applications. The correction filter is placed before the

interpolating filter and can only be used with both FIRs enabled.

Figure 37 shows the magnitude spectrum response for FIR0, a 59-tap interpolating half-band filter. The transition

band is from 0.4 to 0.6 × fIN (the input data rate for the FIR filter) with < 0.002dB of pass-band ripple and > 85 dB

stop-band attenuation. Figure 38 shows the transition band region from 0.36 to 0.46 × fIN. Up to 0.45 × fIN there is

less than 0.5 dB of attenuation.

The DAC sample and hold operation results in the well known sin(x)/x or sinc(x) frequency response shown in

Figure 39 (red line). The DAC3282 has a 5-tap inverse sinc filter (FIR4) placed before the 2x interpolation filter to

compensate for this effect up to 0.2 × fDAC. The inverse sinc filter runs at the input data rate and is operational

only if the 2x interpolation filter is enabled as well, correspondingly the rate of this filter is always half of the DAC

update rate. As a result, the filter cannot completely flatten the frequency response of the sample and hold output

as shown in Figure 39.

Figure 40 shows the magnitude spectrum for FIR4 over the correction range. The inverse sinc filter response

(Figure 40, black line) has approximately the opposite frequency response to sin(x)/x between 0 to 0.2 x fDAC,

resulting in the corrected response in Figure 40 (blue line). Between 0 to 0.2 × fDAC, the inverse sinc filter

compensates for the sample and hold roll-off with less than 0.04-dB error.

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