DS3161 datasheet(75/384 Pages) MAXIM

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DS3161/DS3162/DS3163/DS3164

Figure 8-29 shows a multi-device receive interface unexpected multiple cell transfer. Prior to clock edge 1, the cell

transfer was started. On clock edge 4, since no other PHY device has a cell ready for transfer, the ATM device

assumes another cell transfer from PHY device 'N' and leaves

REN asserted. On clock edge 5, PHY device 'N'

stops transferring cell data and indicates that it does not have another cell ready for transfer by not asserting

RSOX. On clock edge 6, the ATM device deasserts

REN to end the cell transfer process. At the same time, PHY

device 'N' indicates to the ATM device that it now has a complete cell ready for transfer by placing the first byte of

cell data on RDAT, and asserting RSOX to indicate the transfer of the first byte of the cell. On clock edge 7, PHY

device 'N' tri-states its RDAT and RSOX outputs because

REN is deasserted. On clock edge 8, the ATM device

selects PHY device 'N'. On clock edge 9, the ATM device asserts

REN. On clock edge 10, PHY device 'N'

continues the cell transfer by placing the second byte of cell data on RDAT, and deasserting RSOX.

Figure 8-29. UTOPIA Level 2 Receive Unexpected Multiple Cell Transfer

RADR

RPXA

REN

RDAT

RSOX

19 20

RCLK

Transfer

Cell From:

P45 P46 P47 P48

2 3

10 11 12 13 14 15 16 17 18

DS3161 Datasheet(PDF) 75 Page - Maxim Integrated Products