DS3161 datasheet(4/384 Pages) MAXIM

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DS3161/DS3162/DS3163/DS3164

8.3.6

Microprocessor Interface Functional Timing........................................................................................ 85

8.3.7

JTAG Functional Timing....................................................................................................................... 90

INITIALIZATION AND CONFIGURATION

9.1

MONITORING AND DEBUGGING ....................................................................................................................... 93

9.1.1

Cell/Packet FIFO.................................................................................................................................. 93

9.1.2

Cell Processor...................................................................................................................................... 93

9.1.3

Packet Processor ................................................................................................................................. 93

10 FUNCTIONAL DESCRIPTION

10.1 PROCESSOR BUS INTERFACE......................................................................................................................... 94

10.1.1 8/16-Bit Bus Widths.............................................................................................................................. 94

10.1.2 Ready Signal (

RDY) ............................................................................................................................. 94

10.1.3 Byte Swap Modes ................................................................................................................................ 94

10.1.4 Read-Write/Data Strobe Modes........................................................................................................... 94

10.1.5 Clear on Read/Clear on Write Modes .................................................................................................. 94

10.1.6 Global Write Method ............................................................................................................................ 95

10.1.7 Interrupt and Pin Modes....................................................................................................................... 95

10.1.8 Interrupt Structure ................................................................................................................................ 95

10.2 CLOCKS ........................................................................................................................................................ 97

10.2.1 Line Clock Modes................................................................................................................................. 97

10.2.2 Sources of Clock Output Pin Signals ................................................................................................... 98

10.2.3 Line I/O Pin Timing Source Selection .................................................................................................. 99

10.2.4 Clock Structures On Signal IO Pins ................................................................................................... 102

10.2.5 Gapped Clocks................................................................................................................................... 102

10.3 RESET AND POWER-DOWN .......................................................................................................................... 103

10.4 GLOBAL RESOURCES................................................................................................................................... 105

10.4.1 Clock Rate Adapter (CLAD)............................................................................................................... 105

10.4.2 8 kHz Reference Generation ............................................................................................................. 107

10.4.3 One-Second Reference Generation .................................................................................................. 109

10.4.4 General-Purpose I/O Pins.................................................................................................................. 109

10.4.5 Performance Monitor Counter Update Details................................................................................... 111

10.4.6 Transmit Manual Error Insertion ........................................................................................................ 111

10.5 PER PORT RESOURCES ............................................................................................................................... 112

10.5.1 Loopbacks.......................................................................................................................................... 112

10.5.2 Loss Of Signal Propagation ............................................................................................................... 114

10.5.3 AIS Logic............................................................................................................................................ 114

10.5.4 Loop Timing Mode ............................................................................................................................. 116

10.5.5 HDLC Overhead Controller................................................................................................................ 116

10.5.6 Trail Trace .......................................................................................................................................... 117

10.5.7 BERT.................................................................................................................................................. 117

10.5.8 Fractional Payload Controller............................................................................................................. 117

10.5.9 PLCP/Fractional port pins .................................................................................................................. 117

10.5.10 Framing Modes .................................................................................................................................. 121

10.5.11 Mapping Modes.................................................................................................................................. 123

10.5.12 Line Interface Modes.......................................................................................................................... 127

10.6 UTOPIA/POS-PHY/SPI-3 SYSTEM INTERFACE........................................................................................... 128

10.6.1 General Description ........................................................................................................................... 128

10.6.2 Features ............................................................................................................................................. 128

10.6.6 System Interface Bus Controller ........................................................................................................ 129

10.7 ATM CELL / HDLC PACKET PROCESSING.................................................................................................... 134

10.7.1 General Description ........................................................................................................................... 134

10.7.2 Features ............................................................................................................................................. 134

10.7.3 Transmit Cell/Packet Processor......................................................................................................... 135

10.7.4 Receive Cell/Packet Processor.......................................................................................................... 135

10.7.5 Cell Processor.................................................................................................................................... 136

10.7.6 Packet Processor ............................................................................................................................... 141

10.7.7 FIFO ................................................................................................................................................... 143

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