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DS3161 Datasheet(PDF) 1 Page - Maxim Integrated Products |
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DS3161 Datasheet(HTML) 1 Page - Maxim Integrated Products |
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1 / 384 page  1 REV: 113006 Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. GENERAL DESCRIPTION The DS3161, DS3162, DS3163, and DS3164 (DS316x) integrate ATM cell/HDLC packet processor(s) with DS3/E3 framer(s) to map/demap ATM cells or packets into as many as four DS3/E3 digital lines with DS3-framed, E3-framed, or clear- channel data streams on per-port basis. APPLICATIONS Access Concentrators SONET/SDH ADM Multiservice Access Platform (MSAP) SONET/SDH Muxes PBXs Multiservice Protocol Platform (MSPP) Digital Cross Connect Test Equipment ATM and Frame Relay Equipment Routers and Switches Integrated Access Device (IAD) PDH Multiplexer/ Demultiplexer ORDERING INFORMATION PART TEMP RANGE PIN-PACKAGE DS3161 0°C to +70°C 400 TE-PBGA (27mm x 27mm, 1.27mm pitch) DS3161N -40°C to +85°C 400 TE-PBGA (27mm x 27mm, 1.27mm pitch) DS3162 0°C to +70°C 400 TE-PBGA (27mm x 27mm, 1.27mm pitch) DS3162N -40°C to +85°C 400 TE-PBGA (27mm x 27mm, 1.27mm pitch) DS3163 0°C to +70°C 400 TE-PBGA (27mm x 27mm, 1.27mm pitch) DS3163N -40°C to +85°C 400 TE-PBGA (27mm x 27mm, 1.27mm pitch) DS3164 0°C to +70°C 400 TE-PBGA (27mm x 27mm, 1.27mm pitch) DS3164N -40°C to +85°C 400 TE-PBGA (27mm x 27mm, 1.27mm pitch) Note: Add the “+” suffix for the lead-free package option. FUNCTIONAL DIAGRAM CELL/ PACKET PROCESSOR DS316x POS-PHY or UTOPIA DS3/E3 LINE INTERFACE DS3/E3 FRAMER/ FORMATTER FEATURES Single (DS3161), Dual (DS3162), Triple (DS3163), or Quad (DS3164) ATM/Packet PHYs for DS3, E3, and Clear-Channel 52Mbps (CC52) Pin Compatible for Ease of Port Density Migration in the Same PC Board Platform Each Port Independently Configurable Universal PHYs Map ATM Cells and/or HDLC Packets into DS3 or E3 Data Streams UTOPIA L2/L3 or POS-PHY™ L2/L3 or SPI-3 Interface with 8-, 16-, or 32-Bit Bus Width 66MHz UTOPIA L3 and POS-PHY L3 Clock 52MHz UTOPIA L2 and POS-PHY L2 Clock Ports Independently Configurable for Cell or Packet Traffic in POS-PHY Bus Modes Direct, PLCP, DSS, and Clear-Channel Cell Mapping Direct and Clear-Channel Packet Mapping On-Chip DS3 (M23 or C-Bit) and E3 (G.751 or G.832) Framer(s) Ports Independently Configurable for DS3, E3 (Full or Subrate) or Arbitrary Framing Protocols Up to 52Mbps Programmable (Externally Controlled or Internally Finite State Machine Controlled) Subrate DS3/E3 DS3161/DS3162/DS3163/DS3164 Single/Dual/Triple/Quad ATM/Packet PHYs for DS3/E3/STS-1 www.maxim-ic.com POS-PHY and POS-PHY Level 3 are trademarks of PMC-Sierra, Inc. |
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