DS3161 datasheet(19/384 Pages) MAXIM

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DS3161/DS3162/DS3163/DS3164

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Single-bit and multiple-bit header error insertion for diagnostics

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Controls include enables/disables/settings for: cell processing, HEC insertion, coset polynomial addition, cell

scrambling, fill cell type, error insertion type/rate/count, HEC bit corruption

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Counter for number of cells read from the transmit FIFO

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Cell mapping into the DS3/E3 frame, the PLCP frame, an externally defined frame, or the entire line bandwidth

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Octet alignment option for externally defined frame formats

3.11 Transmit Packet Processor Features

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FCS calculation (16-bit or 32-bit) and insertion/overwrite

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Programmable FCS error insertion for diagnostics

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Bit or octet stuffing

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Programmable inter-frame fill insertion (flags or all-ones)

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Automatic packet abort insertion

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Packet scrambling using the self-synchronizing scrambler (x

43+1)

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Controls include enables/disables/settings for: packet processing, FCS insertion or overwrite, 16/32-bit FCS,

inter-frame fill type/length, scrambling, FCS error insertion type/rate/count

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Counters for number of packets and bytes read from the transmit FIFO

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Octet alignment with octet stuffing option for externally defined frame formats

3.12 Transmit PLCP Formatter Features

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Insertion of FAS bytes (A1, A2), path overhead identification (POI) bytes, and path overhead bytes

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Generation of BIP-8 (B1), FEBE and RAI (G1)

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C1 cycle/stuff counter generation referenced to GPIO4 input pin, referenced to the received PLCP timing, or

based on an 8 kHz division of one of the clock sources

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Automatic or manual insertion of FAS errors, BIP-8 errors

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All path overhead fields can be sourced from the PLCP transmit overhead port

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HDLC port for data link messages on F1, M1 or M2 bytes

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Trail Trace port for trace messages on F1 byte

3.13 Transmit DS3/E3 Formatter Features

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Insertion of framing overhead for M23 or C-bit parity DS3,or G.751 E3 or G.832 E3

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B3ZS/HDB3 encoding

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Generation of RDI, AIS, and DS3 idle signal

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Automatic or manual insertion of bipolar violations (BPVs), excessive zeroes (EXZ) occurrences, F-bit errors,

M-bit errors, FAS errors, P-bit parity errors, CP-bit parity errors, BIP-8 errors, and far end block errors (FEBE)

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HDLC port for DS3 path maintenance data link (PMDL), G.751 national bit or G.832 NR or GC channels

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FEAC port for DS3 FEAC channel can be configured to send one codeword, one codeword continuously, or

two different codewords back-to-back to send DS3 Line Loopback commands

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16-byte Trail Trace Buffer port for the G.832 trail access point identifier

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Insertion of G.832 payload type, and timing marker bits from registers

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DS3 M23 C bits configurable as payload or overhead; as overhead they can be controlled from registers or the

transmit overhead port

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Most framing overhead fields can be sourced from transmit overhead port

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Formatter bypass mode for clear channel or externally defined format applications

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Support for subrate DS3/E3, internally or externally controlled (Fractional DS3/E3)

3.14 Clock Rate Adapter Features

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Generation of the internally needed DS3 (44.736 MHz), E3 (34.368 MHz), and STS-1(51.84 MHz) clocks a

from single input reference clock

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Input reference clock can be 51.84 MHz, 44.736MHz or 34.368 MHz

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Derived clocks can be transmitted off-chip for external system use

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Standards compliant jitter and wander requirements.

DS3161 Datasheet(PDF) 19 Page - Maxim Integrated Products

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