DS3161 datasheet(49/384 Pages) MAXIM

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DS3161/DS3162/DS3163/DS3164

TYPE

FUNCTION

TPDENIn /

TPOHENn /

TFOHENIn

Transmit Payload Data Enable Input / PLCP Overhead Enable / Fractional OH Enable

Input /

See Table 10-20.

TPDENIn: When the port is configured for the Flexible fractional mode, this pin is

used to enable payload data from the cell/packet processor. There is a three-clock

delay between TPDENIn and TPDENOn. The signal is sampled on the positive clock

edge of the referenced clock pin if the clock pin signal is not inverted, otherwise it is

sampled on the falling edge of the clock. The signal is typically referenced to the

TCLKIn transmit clock input pins, but it can be referenced to the TLCLKn, TCLKOn,

RCLKOn and RLCLKn clock pins

This signal can be inverted.

TPOHENn: When the port framer is configured for one of the DS3 or E3 PLCP

framing modes, and the port is enabled, this signal will be used the determine which

DS3 or E3 PLCP framing overhead bits to over-write with the signal on the TPOHn

pins. The TPOHSOFn signal marks the start of the framing bit sequence. This signal

is sampled at the same time as the TPOHCLKn signal transitions high to low.

This signal can be inverted.

TFOHENIn: When the port framer is configured for the DS3 or E3 External Fractional

framing, this pin is used to mark the fractional overhead data on the TFOHn pin. The

TSOFOn or TSOFIn pins can be used to select which DS3/E3 payload bits relative to

the start of the DS3/E3 frame to mark. The signal is sampled on the positive clock

edge of the referenced clock pin if the clock pin signal is not inverted, otherwise it is

sampled on the falling edge of the clock. The signal is typically referenced to the

TCLKIn transmit clock input pins, but it can be referenced to the TLCLKn, TCLKOn,

RCLKOn and RLCLKn clock pins

This signal can be inverted.

TCLKOn /

TGCLKn /

TPOHCLKn

Transmit Clock Output / Gapped Clock / PLCP Overhead Clock

See Table 10-22.

TCLKOn: When the port is configured external fractional modes and TCLKOn is

selected, or any other mode and the port pins are enabled and TCLKOn is selected,

this clock output is enabled. This clock is the same clock as the internal framer

transmit clock. This clock is typically used for the reference clock for the TOHMIn /

TSOFIn, TFOHn / TSERn, TFOHENIn and TSOFOn / TDENn / TFOHENOn signals

but can also be used as the reference for the TPOSn / TDATn and TNEGn /

TOHMOn signals.

This signal can be inverted.

DS3: 44.736 MHz +20 ppm

E3: 34.368 MHz +20 ppm

CC52: 52 MHz +20 ppm

TGCLKn: When the port is configured internal fractional mode or any simple DS3/E3

framed mode and the port pins are enabled and TGCLKn is selected, this gated

output clock is enabled. This gapped clock is the same clock as the internal framer

transmit clock and is gated by either TDENn or TFOHENOn depending on which

signal is active. This clock is typically used for the reference clock for the TFOHn /

TSERn signals.

This signal can be inverted.

TPOHCLKn: When the port framer is configured for one of the DS3 or E3 PLCP

framing modes, the port pins are enabled and the TCLKOn pin function is not

selected, this clock is used for the transmit overhead port signals TPOHn, TPOHENn

and TPOHSOFn. The TPOHSOFn output signal is updated and the TPOHn and

TPOHENn input signals are sampled at the same time this clock signal transitions

from high to low. The external logic is expected to sample TPOHSOFn signal and

update the TPOHn and TPOHENn signals on the rising edge of this clock signal. This

clock is a low frequency clock.

This signal can be inverted.

TSOFOn /

Transmit PLCP Overhead Start Of Frame / Framer Start Of Frame /Data Enable

DS3161 Datasheet(PDF) 49 Page - Maxim Integrated Products

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