DS3161 datasheet(91/384 Pages) MAXIM

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DS3161/DS3162/DS3163/DS3164

9 INITIALIZATION AND CONFIGURATION

STEP 1: Check Device ID Code:

Before any testing can be done, device ID code, which is stored in GL.IDR, shoud be checked against device ID

codes shown below to ensure correct device is being used.

Current device ID codes are:

DS3161 rev 1.0:

0x40h

DS3162 rev 1.0:

0x41h

DS3163 rev 1.0:

0x42h

DS3164 rev 1.0:

0x43h

STEP 2: Initialize the Device.

Before configuring for operation, make sure the device is in a known condition with all registers set to their default

value by initiating a Global Reset. (See Section 10.3) A Global Reset can be initiated via the RST pin or by the

Global Reset bit (GL.CR1.RST). A Port Reset is not necessary since the global reset includes a reset of all ports to

their default values.

STEP 3: Clear the Reset.

It is necessary to clear the RST bit to begin normal operation.

After clearing the RST bit, the device is configured for default mode.

Default mode:

System Interface: UTOPIA Level 2, 8-bit databus

Framer: C-bit DS3

STEP 4: Clear the Data Path Resets and the Port Power-Down bit.

The default value of the Data Path Resets is one, which keeps the internal logic in the reset status. The user

needs to clear the following bits:

GL.CR1.RSTDP = 0

PORT.CR1.RSTDP = 0

PORT.CR1.PD = 0

STEP 5: Select the clock source.

Loop Time (use the receive clock (RLCLKn)): Set PORT.CR3.LOOPT = 1

CLAD Source: Set PORT.CR3.CLADC = 0

TCLKI Source: Set PORT.CR3.CLADC = 1

If using the CLAD, properly configure the CLAD by setting the CLAD bits in GL.CR2.

STEP 6: Configure the Framing Mode and the Line Mode.

PORT.CR2.LM = 0 (AMI/B3ZS/HDB3 Interface) or another setting. See Table 10-31

PORT.CR2.FM[5:0] set to the correct framing mode. See Table 10-30.

STEP 7: Disable Payload AIS (downstream AIS) and Line AIS

PORT.CR1.PAIS[2:0] = 111

PORT.CR1.LAIS[1:0] = 11

STEP 8: Initialize and configure the FIFOs.

Reset the Transmit and Receive FIFO. FF.TCR.TFRST = 1. FF.RCR.RFRST = 1.

Clear the FIFO Reset bits. FF.TCR.TFRST = 0. FF.RCR.RFRST = 0.

Set the FIFO Transmit Level Control Register and the FIFO Transmit Port Address Control Register.

Set the FIFO Receive Level Control Register and the FIFO Receive Port Address Control Register.

The Port Address needs to be configured to match the master controller address for each port.

DS3161 Datasheet(PDF) 91 Page - Maxim Integrated Products

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