DS3161 datasheet(84/384 Pages) MAXIM

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DS3161/DS3162/DS3163/DS3164

8.3.5.4

POS-PHY Level 3 Functional Timing

Figure 8-38 shows a multi-port transmit interface multiple packet transfer to different PHY ports. On clock edge 1,

PHY port 'N' indicates to the POS device that it can accept a block of packet data by asserting TPXA. On clock

edge 3, the POS device selects PHY port 'N' by placing its address on TDATA and asserting TSX while

TEN is de-

asserted. On clock edge 4, the POS device starts a packet transfer to PHY port 'N' by de-asserting TSX, asserting

TEN, placing the first byte of packet data on TDATA, and asserting TSOX to indicate the transfer of the first byte of

the packet. On clock edge 5, the POS device de-asserts TSOX as it continues to place additional bytes of the

packet on TDATA and PHY port 'N' asserts TSPA. On clock edge 11, the POS device polls PHY port 'L'. On clock

edge 12, PHY port 'N' indicates that it cannot accept any more data transfers by de-asserting TSPA. On clock edge

13, PHY port 'L' indicates to the POS device that it can accept a block of packet data by asserting TPXA. On clock

edge 14, the POS device de-asserts

TEN to end the packet transfer process to PHY port 'N' and selects PHY port

'L' by placing its address on TDATA and asserting TSX while

TEN is de-asserted. On clock edge 15, the POS

device starts a packet transfer to PHY port 'L' by asserting

TEN, de-asserting TSX, placing the first byte of packet

data on TDATA, and asserting TSOX to indicate the transfer of the first byte of the packet. On clock edge 16, the

POS device de-asserts TSOX as it continues to place additional bytes of the packet on TDATA and PHY port 'L'

asserts TSPA.

Figure 8-38. POS-PHY Level 3 Transmit Multiple Packet Transfer In-Band Addressing

P39

P38

P40

P41

P42

TCLK

TADR

TPXA

TEN

TEOP

TERR

TDAT

Transfer

To PHY

TSPA

P43

TSOX

P44

TSX

…

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