DS3161 datasheet(2/384 Pages) MAXIM

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DS3161/DS3162/DS3163/DS3164

FEATURES (continued)

Full-Featured DS3/E3/PLCP Alarm Generation

and Detection

Built-In HDLC Controllers with 256-Byte FIFOs

for Insertion/Extraction of DS3 PMDL, G.751 Sn

Bit, and G.832 NR/GC Bytes and PLCP NR/GC

Bytes

On-Chip BERTs for PRBS and Repetitive Pattern

Generation, Detection, and Analysis

Large Performance-Monitoring Counters for

Accumulation Intervals of at Least 1 Second

Flexible Overhead Insertion/Extraction Ports for

DS3, E3, and PLCP Framers

Pin and Software Compatible with DS3181–

DS3184 Single–Quad ATM/Packet PHYs with

Built-In LIUs and DS3171–DS3174 Single–Quad

DS3/E3 Single-Chip Transceivers—Framers and

LIUs

DETAILED DESCRIPTION

The DS3161 (single), DS3162 (dual), DS3163 (triple), and DS3164 (quad) PHYs perform all the functions

necessary for mapping/demapping ATM cells and/or packets into as many as four DS3 (44.736Mbps) framed, E3

(34.368Mbps) framed, or 52Mbps clear-channel data streams. Dedicated cell processor and packet processor

blocks prepare outgoing cells or packets for transmission and check incoming cells or packets upon arrival. Built-in

DS3/E3 framers transmit and receive cell/packet data in properly formatted M23 DS3, C-bit DS3, G.751 E3, or

G.832 E3 data streams. PLCP framers provide legacy ATM transmission-convergence support. DSS scrambling is

performed for clear-channel ATM cell support. With integrated hardware support for both cells and packets, the

DS316x DS3/E3 ATM/Packet PHYs provide system-on-chip solutions (from DS3/E3/STS-1 digital lines to

ATM/Packet UTOPIA/POS-PHY Level 2/3 system switch) for universal high-density line cards in the unchannelized

DS3/E3/clear-channel DS3 ATM/Packet applications. Unused functions can be powered down to reduce device

power. The DS316x ATM/Packet PHYs with embedded framers conform to the telecommunications standards

listed in Section 4.

1 BLOCK DIAGRAM

Figure 1-1 shows the functional block diagram of one channel ATM/Packet PHY.

Figure 1-1. DS316x Functional Block Diagram

IEEE P1149.1

JTAG Test

Access Port

Microprocessor

Interface

HDLC

FEAC

DS3 / E3

Transmit

Formatter

DS3 / E3

Receive

Framer

Trail

Trace

Buffer

Tx Cell

Processor

FIFO

Cell

Processor

FIFO

Tx Packet

Processor

Packet

Processor

TAIS

TUA1

FRAC/

PLCP

RX FRAC/

PLCP

Clock

Rate

Adapter

TX BERT

RX BERT

UA1

GEN

B3ZS/

HDB3

Encoder

B3ZS/

HDB3

Decoder

TSCLK

TADR[4:0]

TDATA[31:0]

TPRTY

TEN

TDXA[4:2]

TSOX

TEOP

TSPA

TSX

TMOD[1:0]

TERR

RSCLK

RADR[4:0]

RDATA[31:0]

RPRTY

REN

RDXA[4:2]

RSOX

REOP

RVAL

RMOD[1:0]

RERR

TDXA[1]/TPXA

/RSX

n = port #

RLCLKn

TPOSn/

TDATn

TNEGn/

TOHMOn/

TLCLKn

RDATn

RPOSn/

RNEGn/

RLCVn/

ROHMIn

DS316x

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