DS3161 datasheet(95/384 Pages) MAXIM

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DS3161/DS3162/DS3163/DS3164

The clear on read mode is simpler since the bits that were read as being set will be cleared automatically. This

method will work well in a software system where multiple tasks do not read the same latched status register. The

latched status register bits in clear on read mode are carefully designed not to miss events that occur while a

10.1.6 Global Write Method

All of the ports can be written to simultaneously using the global write method. This method is enabled by setting

the GL.CR1.GWM bit. When the global write method is enabled, a write to a register on any valid port will write to

the same register on all valid ports. A valid port is a port that is available in a particular packaged part. For

example, port four would not be valid in a DS3163 device. After reset, the global write method is not enabled.

When the GWM bit is set, read data from the port registers is not valid and read data from the global and test

registers is valid. The data value read back from a port register should be ignored.

10.1.7 Interrupt and Pin Modes

The interrupt (

INT) pin is configurable to drive high or float when not active. The GL.CR1.INTM bit controls the pin

configuration, when it is set the

INT pin will drive high when not active. After reset, the INT pin will be in high-

impedance mode until an interrupt source is active and enabled to drive the interrupt pin.

10.1.8 Interrupt Structure

The interrupt structure is designed to efficiently guide the user to the source of an enabled interrupt source. The

status bits in the global status (GL.SR) and global status latched register (GL.SRL) are read to determine if the

interrupt source is a global event like the UTOPIA/POS-PHY interface, global performance monitor update or

whether it came from one of the ports. If the interrupt event came from one of the ports then the port status register

(PORT.SR) and port status register latched (PORT.SRL) can be read to determine if the interrupt source is a

common port event like the performance monitor update or whether it came from one of the DS3/E3 Framers,

PLCP Framer, ATM/PKT, BERT, HDLC, FEAC or Trail Trace status registers. If the interrupt came from one of the

DS3/E3 Framers, PLCP Framer, ATM/PKT, BERT, HDLC, FEAC or Trail Trace status registers, then one of those

registers will need to be read to determine the event that caused the interrupt.

The source of an interrupt can be determined by reading three status registers: global, port and block status

registers.

When a mode is not enabled, then interrupts from that source will not occur. For example, if PLCP framing is not

enabled then the potential interrupts from the latched status register in the PLCP block cannot occur. Similarly, if

E3 framing mode is enabled, an interrupt source that is defined in DS3 framing, but not in E3 framing, cannot

create a new interrupt. Note that when modes are changed, the latched status bits of the new mode, as well as any

other mode, may get set. If the data path reset is set during or after the mode change, the latched status bits will be

automatically cleared. If the data path reset is not used to clear the latched status bits, then the registers must be

cleared by reading or writing to them based on the register clear method selected.

DS3161 Datasheet(PDF) 95 Page - Maxim Integrated Products