6402 datasheet(195/250 Pages) INTEL

195 / 250 page

Intel® 6400/6402 Advanced Memory Buffer Datasheet

195

Registers

Note:

In the later half part of data burst length 8 test, 144 bits or 288 bits user-defined data pattern will be repeat as the same

sequence of burst length 4.

14.5.2.3.1

MBDATA Failure Address Mapping

To compress the failure address into 32 bits, bits that are always zero are removed

from the logging. These removed bits include AutoPrecharge Column address [10] and

least significant bits assumed by burst length.

BL4: 1 bit chunk indicates the location of 2 failure burst data chunks.

The above Column plus Chunk is equal to DRAM column address as the following:

• where the auto-precharge address bit 10 is assumed zero

• since data is logged in 144 bits (two chunks), address bit zero is not needed

BL8: 2 bit chunk indicates the location of 4 failure burst data chunks.

The above Column plus Chunk is equal to DRAM column address as the following:

MBDATA2 31:0

50h

Late data [31:0]

Failure bit location

accumulator

Fail address 3

Late data [31:0]

Failure bit location

accumulator

Fail address 3

Late data [31:0]

Failure bit location

accumulator

Fail address 3

Late data [31:0]

Failure bit location

accumulator

User defined Late

data [31:0] (1st

burst data)

MBDATA1 31:0

4Ch

Early data [63:32]

Failure bit location

accumulator

Fail address 2

Early data [63:32]

Failure bit location

accumulator

Fail address 2

Early data [63:32]

Failure bit location

accumulator

Fail address 2

Early data [63:32]

Failure bit location

accumulator

User defined Early

data [63:32]

(1st burst data)

MBDATA0 31:0

48h

Early data [31:0]

Failure bit location

accumulator

Fail address 1

Early data [31:0]

Failure bit location

accumulator

Fail address 1

Early data [31:0]

Failure bit location

accumulator

Fail address 1

Early data [31:0]

Failure bit location

accumulator

User defined Early

data [31:0]

(1st burst data)

Reg

Bit

Offset

Description by mode

(note: MBCSR.dtype, MBCSR.mbdata and MBCSR.enable288 select mode)

Fixed Data

Pattern

144 bit User

Defined Pattern

Circular Shift

LFSR

288 bit User

defined pattern

Table 14-11. MBDATA Failure Address Register Correspondence to DRAM Address

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

see description below

Bank

Row

Column and Chunk

Table 14-12. BL4 Column and Chunk Correspondence to DRAM Address

DRAM Col Address

Data Chunk

6402 Datasheet(PDF) 195 Page - Intel Corporation

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