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6402 Datasheet(PDF) 193 Page - Intel Corporation |
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6402 Datasheet(HTML) 193 Page - Intel Corporation |
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193 / 250 page ![]() Intel® 6400/6402 Advanced Memory Buffer Datasheet 193 Registers Algorithms: When Embedded algorithm is applied, please program the following bits at the same time. 1. Select MBCSR.cmd bit[5:4] for the initial command execution mode. For all algorithm choices except for Data Retention Read, select "01: write only". For Data Retention Read, select "10: read with data comparison". 2. Program MBCSR.fast bit[11:10] to select FastX, FastY, FastXY, or XZY. 3. Program proper start/end address registers and corresponding MTR value for DIMM type. Do not leave start and end address register as default "00" or the same value. Algorithm does not support single or full address modes. 14.5.2.2 MBADDR: Memory Test Address The register is used by MemBIST only when testing to a single memory location. (MBCSR.atype = 2b‘01) 11:10 RW 00 FAST: Address sequencing 00 => addressing with XZY toggling (column->bank->row) 01 => Fast Y with fixed bank 10 => Fast X with fixed bank 11 => Fast XY with fixed bank 9:8 RW 00 DTYPE: Data type selection: 00 => Fixed data pattern, selected by MBCSR bits 18:16 01 => 144 or 288 bits user defined data 10 => Circular shift data 11 => LFSR data, seeded from 32 bit LFSR seed register. Note: Algorithm mode only supports DTYPE = Fixed Note: Circular shift data and LFSR data type should not be used for single address operation (ATYPE = 01). 7:6 RW 00 ATYPE: Address type 00 => Reserved 01 => Single physical address operation, contained in MBADDR row/column/ bank. 10 => start/end physical address range defined in MB_START_ADDR & MB_END_ADDR registers. • In FastX, FastY and FastXY modes, only the bank specified in MB_START_ADDR will be exercised. 11 => full address range of the DIMM as defined in MTR register which specifies the number of banks, rows, and columns. • In FastX, FastY and FastXY modes, only the bank 0 will be exercised. 5:4 RW 00 CMD: Command execution: 00 => Read only without data comparison 01 => Write only 10 => Read with data comparison 11 => Write followed by Read with data comparison 3:0 RV 0 Reserved Device: NodeID Function: 3 Offset: 40h Bit Attr Default Description |
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