6402 datasheet(190/250 Pages) INTEL

190 / 250 page

Registers

190

Intel® 6400/6402 Advanced Memory Buffer Datasheet

27:24

RWST

CLKDIS: clock[3:0] output disable

RWST

SEQADDR: When set to 1 turns off address balancing on address bit A0 to support

DRAMs programmed for Sequential Burst Type

RWST

DQSHALFGAIN: - select for DQS differential amplifier gain. When set to 0

the amplifier gain is cut half to support differential strobes for DDR2

Note: the sense of this field is inverted from past DDR designs so that BIOS

supporting generic AMBs do not have to write a “1” to what is a “reserved”

field on other AMBs

TESTMODE: When set to 1 the LEGSEL output of the DDR comp block selects one

of eight driver legs to enable. This bit can be used in conjunction with the

DRAMISCTL.DRVOVR bits to override the LEGSEL output generated by the comp

block.

RWST

RWPRDIS: Read/Write pointer reset disable

Disables the resetting of DDR cluster FIFO read and write pointers during normal

operation that occurs when a READ command finishes executing and no additional

READ commands are in process.

RWST

ODTZ: On-Die Termination Strength.

“0”

Disabled

“1”

Enabled

RWST

HLDDIS: command/address hold disable

Disabling hold will allow the address and bank address pins to revert to all zeros (all

ones on the balanced address copy) during idle cycles. When hlddis is clear, the

addresses retain the value of the last non-idle command cycle in order to reduce

switching on the bus.

RWST

BALDIS: command/address balancing disable

CADIS: command/address output disable

CSDIS: chip select output disable

ODTDIS: ODT output disable

RWST

CKEFRCLOW: CKE Force Low

Forces CKE low. Must be cleared to enable normal DDR functionality. This bit

overrides the CKE1 and CKE0 fields described below, and also overrides all channel

commands and other hardware functions that would otherwise affect the state of

the CKE outputs.

CKEDIS: CKE output disable

RWST

CKE1: CKE output 1 control and status. Software can write to this bit to change the

state of the CKE 1 output. Hardware will update this bit with the current status of

the CKE1 output two core cycles after a channel command or other hardware

function changes the state of the CKE1 output.

‘1’ = CKE1 pads asserted.

‘0’ = CKE1 pads de-asserted.

9RWST

CKE0: CKE output 0 control and status. Software can write to this bit to change the

state of the CKE 0 output. Hardware will update this bit with the current status of

the CKE 0 output two core cycles after a channel command or other hardware

function changes the state of the CKE 0 output.

‘1’ = CKE0 pads asserted.

‘0’ = CKE0 pads de-asserted.

8RWST

BL: DRAM burst length.

‘1’ = bl8

‘0’ = bl4

7:4

RWST

AL: DRAM Additive Latency [3:0]

Note: This AL value is sampled during TS2 training sequences to set timing for FBD

link data returns. Changes to AL after this time will not effect FBD link data return

timing until the next TS2 sequence following link reset.

Device:

NodeID

Function: 3

Offset:

7Ch

Bit

Attr

Default

Description

6402 Datasheet(PDF) 190 Page - Intel Corporation

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