6402 datasheet(187/250 Pages) INTEL

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Intel® 6400/6402 Advanced Memory Buffer Datasheet

187

Registers

14.5.1.4

DRT: DRAM Timing Control

The DRAM Timing Control register is used to setup timing for MemBIST access to

DRAMs.

RWST

NUMRANK: Technology – Number of Ranks

Define the number of ranks within these DIMM’s

0 = single ranked

1 = double ranked

RWST

NUMBANK: Technology – Number of Banks

Define the number of banks within these DIMM’s

0 = 4 banks

1 = 8 banks

3:2

RWST

NUMROW: Technology – Number of Rows

Define the number of rows within these DIMM’s

00 = 8,192

01 = 16,384

10 = 32,768

11 = 65,536

1:0

RWST

NUMCOL: Technology – Number of Columns

Define the number of columns within these DIMM’s

00 = 1,024

01 = 2,048

10 = 4,096

11 = 8,192

Device:

NodeID

Function: 3

Offset:

77h

Bit

Attr

Default

Description

Device:

NodeID

Function: 3

Offset:

78h

Bit

Attr

Default

Description

Reserved

30:29

RWST

TRAS: DRAM tRAS minimum required delay from active command to precharge

command. Delay cycles based on JEDEC DDRII spec 45 ns for DDRII 400/533/667.

Based on the latest JEDEC spec (JESD79-2, Sept 2003) for DDRII 800 MHz min

tRAS is not defined yet.

tRASMIN clocks delay:

00 => 18 for DDRII 800 MHz

01 => 15 for DDRII 667 MHz

10 => 12 for DDRII 533 MHz

11 => Reserved

28:27

RWST

TRTP: DRAM cell internal read to precharge command delay.

tRTP clocks delay:

00 => 2

01 => 3

10 => 4

11 => 5

6402 Datasheet(PDF) 187 Page - Intel Corporation

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