6402 datasheet(188/250 Pages) INTEL

188 / 250 page

Registers

188

Intel® 6400/6402 Advanced Memory Buffer Datasheet

26:24

RWST

000

BBRW: Back to Back Read-Write turn around.

This field determines the minimum number of CMDCLK between Read-Write

commands. The purpose of these 3 bits are to control the turnaround time on the

DQ bus.

Regular setting will be based on BL/2 + 2 tCK.

BL4: tR2W = 4 tCK

BL8: tR2W = 6 tCK

Command clocks apart based on the following encoding:

000 => 10

001 => 9

010 => 8

011 => 7

100 => 6

101 => 5

110 => 4

111 => 3 (stress mode, not recommended)

Reserved

22:20

RWST

000

BBWR: Back to Back Write-Read turn around.

This field determines the minimum number of CMDCLK between Write-Read

commands. The purpose of these 3 bits are to control the turnaround time on the

DQ bus.

Regular setting will be based on (CL-1)+BL/2+tWTR.

Command clocks apart based on the following encoding:

000 => 12

001 => 11

010 => 10

011 => 9

100 => 8

101 => 7

110 => 6

111 => 5 (stress mode, not recommended

Reserved

18:16

RWST

000

TWR: Twr DRAM Write Recovery delay

Overall delay clocks will be (CL+AL-1) +BL/2 + tWR from write command to

precharge command.

000 => 9

001 => 8

010 => 7

011 => 6

100 => 5

101 => 4

110 => 3

111 => 2

Device:

NodeID

Function: 3

Offset:

78h

Bit

Attr

Default

Description

6402 Datasheet(PDF) 188 Page - Intel Corporation

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