6402 datasheet(186/250 Pages) INTEL

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Registers

186

Intel® 6400/6402 Advanced Memory Buffer Datasheet

14.5

DDR and Miscellaneous Registers (Function 3)

14.5.1

Memory Registers

14.5.1.1

DAREFTC: DRAM Auto-Refresh Timing and Control

14.5.1.2

DSREFTC: DRAM Self-Refresh Timing and Control

14.5.1.3

MTR: Memory Technology Register

This register provides a local definition of the organization of DIMMs. This DRAM

configuration information is used for MemBIST and DDR calibration.

Device:

NodeID

Function: 3

Offset:

70h

Bit

Attr

Default

Description

Reserved

RWST

REFDERR: refresh buffer overflow error

RWST

REFIERR: buffer count greater than the number of installed ranks

RWST

ORIDEHS: override handshake; auto-refresh wins arbitration for

command bus

27:24

RWST

RBUF: number of pending refreshes for all ranks combined

23:16

RWST

4Eh

TRFC: DRAM refresh period

AREFEN: auto-refresh enable

14:0

RWST

0C30h

TREFI: DRAM refresh interval

Device:

NodeID

Function: 3

Offset:

74h

Bit

Attr

Default

Description

23:17

Reserved

RWST

DISSREXIT: Disable DRAM Self-Refresh Exit when the link comes up

15:8

RWST

56h

TXSNR: DRAM Self-Refresh Exit to Non-Read Command Timing

7:4

RWST

TRP: DRAM Precharge Timing

3RV

Reserved

2:0

RWST

TCKE: DRAM Minimum CKE Pulse Width

Device:

NodeID

Function: 3

Offset:

77h

Bit

Attr

Default

Description

7RV

Reserved

RWST

WIDTH: Technology – DRAM data width

Define the data width of SDRAMs within these DIMM’s

0 = x4 (4 bits wide)

1 = x8 (8 bits wide)

6402 Datasheet(PDF) 186 Page - Intel Corporation

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