AM3871 datasheet(171/345 Pages) TI1

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SPRS695

– SEPTEMBER 2011

All SRAM located in a switchable power domain (all domains except ALWAYS_ON) automatically enters

SHUTDOWN mode whenever its associated power domain goes into the "OFF" state. The SRAM returns

to the ACTIVE state when the corresponding Power Domain returns to the "ON" state.

In addition, the following SRAM within the ALWAYS_ON Power Domain can also be independently put

into SHUTDOWN by programming the x_MEM_PWRDN registers in the Control Module:

•

Media Controller SRAM

•

OCMC SRAM

For detailed instructions on powering up/down the various device SRAM, see the TBD chapter of the

AM387x Sitara ARM Microprocessors (MPUs) Technical Reference Manual (Literature Number:

SPRUGZ7).

7.2.4

SERDES_CLKP/N LDO

The SERDES_CLKP/N input buffers are powered by an internal LDO which is programmed through the

REFCLK_LJCBLDO_CTRL register in the Control Module.

For more information on programming the SERDES_CLKN/P LDO, see TBD chapter of the AM387x Sitara

ARM Microprocessors (MPUs) Technical Reference Manual (Literature Number: SPRUGZ7).

7.2.5

Dual Voltage I/Os

The device supports dual voltages on some of its I/Os. These I/Os are partitioned into the following

groups, and each group has its own dedicated supply pins: DVDD, DVDD_GPMC, DVDD_C, DVDD_SD,

and DVDD_M. The supply voltage for each group can be independently powered with either 1.8 V or

3.3 V.

For the mapping between pins and power groups, see Section 3.2, Terminal Functions of the datasheet.

In addition, the I/O voltage on each DDR interface is independently selectable between either 1.5 V or 1.8

V to support various DDR device types. The I/O supplies for each DDR interface are separate and isolated

to allow populating different memory types on each interface.

7.2.6

I/O Power-Down Modes

On the device, there are power-down modes available for the following PHYs:

•

Video DAC

•

DDR

•

USB

•

HDMI

•

PCIE

•

SATA

When a PHY controller is in a power domain that is to be turned "OFF", software must configure the

corresponding PHY into power-down mode, prior to putting the power domain in the "OFF" state.

Power, Reset, Clocking, and Interrupts

171

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