AM3871 datasheet(172/345 Pages) TI1

172 / 345 page

AM3874, AM3872, AM3871

SPRS695

– SEPTEMBER 2011

www.ti.com

7.2.7

Standby and Deep Sleep Modes

The device supports Low-Power Standby and Deep-Sleep Modes as described below.

Standby Mode is defined as a state in which:

•

All switchable power domains are in "OFF" state

•

The ARM Cortex-A8 is executing an IDLE loop at its lowest frequency of operation

•

All functional blocks not needed for a given application are clock gated

Deep Sleep Mode is defined to be the same as Standby Mode, with the addition of gating the crystal

oscillator to further eliminate all active power. The device core voltages can be reduced to 0.83 V for

optimal power savings.

For detailed instructions on entering and exiting from Standby and Deep Sleep Modes, see the Power,

Reset, and Clock Management (PRCM) Module chapter of the AM387x Sitara ARM Microprocessors

(MPUs) Technical Reference Manual (Literature Number: SPRUGZ7).

7.2.8

Supply Sequencing

The device power supplies are organized into four Supply Sequencing Groups:

1. All CVDD supplies (CVDD, CVDD_x)

2. All 1.5-V Supplies (DVDD_DDR[x] at 1.5 V [only needed if using DDR3])

3. All 1.8-V Supplies (DVDD_x, DVDD_M, DVDD_DDR[x] at 1.8 V [if using LPDDR, DDR2],

VDDA_x_1P8, VDDA_1P8)

4. All 3.3-V Supplies (DVDD, DVDD_x, DVDD_C, VDDA_x_3P3)

To ensure proper device operation, a specific power-up and power-down sequence must be followed.

Some TI power-supply devices include features that facilitate these power sequencing requirements

— for

example, TI

’s TPS659113 integrated PMIC. For more information on TI power supplies and their features,

visit www.ti.com/processorpower.

For more detailed information on the actual power supply names and their descriptions, see Table 3-49,

Supply Voltages Terminal Functions.

7.2.8.1

Power-Up Sequence

For proper device operation, the following power-up sequence in Table 7-6 and Figure 7-1 must be

followed.

Table 7-6. Power-Up Sequence Ramping Values

NO.

DESCRIPTION

MIN

MAX

UNIT

1.8 V supplies to 3.3 V supplies

(1)

1.8 V supplies to 1.5 V (DVDD_DDR[x]) supplies

0(2)

1.8 V supplies stable to CVDD, CVDD_x supplies ramp start

0(2)

Master

All supplies valid to power-on-reset (POR high)

4 096

Clocks

(1)

The 3.3 V supplies must never be more than 2 V above the 1.8 V supplies (see Figure 7-2).

(2)

The 1.8 V supplies must be

≥ 1.5 V (DVDD_DDR[x]) and CVDD, CVDD_x supplies.

172

Power, Reset, Clocking, and Interrupts

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