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AM1802 Datasheet(PDF) 110 Page - Texas Instruments

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Part # AM1802
Description  AM1802 ARM Microprocessor
PDF  180 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

AM1802 Datasheet(HTML) 110 Page - Texas Instruments

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AM1802
SPRS710C – NOVEMBER 2010 – REVISED MARCH 2012
www.ti.com
Table 5-47. Switching Characteristics for McASP0 (1.2V, 1.1V)(1)
1.2V
1.1V
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
9
tc(AHCLKRX)
Cycle time, AHCLKR/X
25
28
ns
10
tw(AHCLKRX)
Pulse duration, AHCLKR/X high or low
AH - 2.5(2)
AH - 2.5(2)
ns
11
tc(ACLKRX)
Cycle time, ACLKR/X
ACLKR/X int
25(3)(4)
28(3)(4)
ns
12
tw(ACLKRX)
Pulse duration, ACLKR/X high or low
ACLKR/X int
A - 2.5(5)
A - 2.5(5)
ns
ACLKR/X int
-1
6
-1
8
ns
Delay time, ACLKR/X transmit edge
13
td(ACLKRX-AFSRX)
ACLKR/X ext input
2
13.5
2
14.5
ns
to AFSX/R output valid(6)
ACLKR/X ext output
2
13.5
2
14.5
ns
ACLKR/X int
-1
6
-1
8
ns
Delay time, ACLKX transmit edge to
14
td(ACLKX-AXRV)
ACLKR/X ext input
2
13.5
2
15
ns
AXR output valid
ACLKR/X ext output
2
13.5
2
15
ns
Disable time, ACLKR/X transmit
ACLKR/X int
0
6
0
8
ns
15
tdis(ACLKX-AXRHZ)
edge to AXR high impedance
ACLKR/X ext
2
13.5
2
15
ns
following last data bit
(1)
McASP0 ACLKX0 internal - ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX0 external input - McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX0 external output - McASP0ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR0 internal - McASP0 ACLKR0CTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR0 external input - McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR0 external output - McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2)
AH = (AHCLKR/X period)/2 in ns. For example, when AHCLKR/X period is 25 ns, use AH = 12.5 ns.
(3)
P = SYSCLK2 period
(4)
This timing is limited by the timing shown or 2P, whichever is greater.
(5)
A = (ACLKR/X period)/2 in ns. For example, when AHCLKR/X period is 25 ns, use AH = 12.5 ns.
(6)
McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0
Table 5-48. Switching Characteristics for McASP0 (1.0V)(1)
1.0V
NO.
PARAMETER
UNIT
MIN
MAX
9
tc(AHCLKRX)
Cycle time, AHCLKR/X
35
ns
10
tw(AHCLKRX)
Pulse duration, AHCLKR/X high or low
AH - 2.5(2)
ns
11
tc(ACLKRX)
Cycle time, ACLKR/X
ACLKR/X int
35(3)(4)
ns
12
tw(ACLKRX)
Pulse duration, ACLKR/X high or low
ACLKR/X int
A - 2.5(5)
ns
ACLKR/X int
-0.5
10
ns
Delay time, ACLKR/X transmit edge to AFSX/R output
13
td(ACLKRX-AFSRX)
ACLKR/X ext input
2
19
ns
valid(6)
ACLKR/X ext output
2
19
ns
ACLKR/X int
-0.5
10
ns
14
td(ACLKX-AXRV)
Delay time, ACLKX transmit edge to AXR output valid
ACLKR/X ext input
2
19
ns
ACLKR/X ext output
2
19
ns
ACLKR/X int
0
10
ns
Disable time, ACLKR/X transmit edge to AXR high
15
tdis(ACLKX-AXRHZ)
impedance following last data bit
ACLKR/X ext
2
19
ns
(1)
McASP0 ACLKX0 internal - ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX0 external input - McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX0 external output - McASP0ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR0 internal - McASP0 ACLKR0CTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR0 external input - McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR0 external output - McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2)
AH = (AHCLKR/X period)/2 in ns. For example, when AHCLKR/X period is 25 ns, use AH = 12.5 ns.
(3)
P = SYSCLK2 period
(4)
This timing is limited by the timing shown or 2P, whichever is greater.
(5)
A = (ACLKR/X period)/2 in ns. For example, when AHCLKR/X period is 25 ns, use AH = 12.5 ns.
(6)
McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0
110
Peripheral Information and Electrical Specifications
Copyright © 2010–2012, Texas Instruments Incorporated
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