AM1802 datasheet(117/180 Pages) TI1

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AM1802

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SPRS710C – NOVEMBER 2010 – REVISED MARCH 2012

Table 5-51. General Timing Requirements for SPI0 Slave Modes(1)

1.2V

1.1V

1.0V

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

tc(SPC)S

Cycle Time, SPI0_CLK, All Slave Modes

40(2)

50(2)

60(2)

tw(SPCH)S

Pulse Width High, SPI0_CLK, All Slave Modes

tw(SPCL)S

Pulse Width Low, SPI0_CLK, All Slave Modes

Polarity = 0, Phase = 0,

to SPI0_CLK rising

Polarity = 0, Phase = 1,

Setup time, transmit data

to SPI0_CLK rising

written to SPI before initial

tsu(SOMI_SPC)S

clock edge from

Polarity = 1, Phase = 0,

master.(3) (4)

to SPI0_CLK falling

Polarity = 1, Phase = 1,

to SPI0_CLK falling

Polarity = 0, Phase = 0,

from SPI0_CLK rising

Polarity = 0, Phase = 1,

Delay, subsequent bits valid from SPI0_CLK falling

td(SPC_SOMI)S

on SPI0_SOMI after

Polarity = 1, Phase = 0,

transmit edge of SPI0_CLK

from SPI0_CLK falling

Polarity = 1, Phase = 1,

from SPI0_CLK rising

Polarity = 0, Phase = 0,

0.5S-6

0.5S-16

0.5S-20

from SPI0_CLK falling

Polarity = 0, Phase = 1,

0.5S-6

0.5S-16

0.5S-20

Output hold time,

from SPI0_CLK rising

toh(SPC_SOMI)S SPI0_SOMI valid after

Polarity = 1, Phase = 0,

receive edge of SPI0_CLK

0.5S-6

0.5S-16

0.5S-20

from SPI0_CLK rising

Polarity = 1, Phase = 1,

0.5S-6

0.5S-16

0.5S-20

from SPI0_CLK falling

Polarity = 0, Phase = 0,

1.5

to SPI0_CLK falling

Polarity = 0, Phase = 1,

1.5

Input Setup Time,

to SPI0_CLK rising

tsu(SIMO_SPC)S SPI0_SIMO valid before

Polarity = 1, Phase = 0,

receive edge of SPI0_CLK

1.5

to SPI0_CLK rising

Polarity = 1, Phase = 1,

1.5

to SPI0_CLK falling

Polarity = 0, Phase = 0,

from SPI0_CLK falling

Polarity = 0, Phase = 1,

Input Hold Time,

from SPI0_CLK rising

tih(SPC_SIMO)S

SPI0_SIMO valid after

Polarity = 1, Phase = 0,

receive edge of SPI0_CLK

from SPI0_CLK rising

Polarity = 1, Phase = 1,

from SPI0_CLK falling

(1)

P = SYSCLK2 period; S = tc(SPC)S (SPI slave bit clock period)

(2)

This timing is limited by the timing shown or 3P, whichever is greater.

(3)

First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on

SPI0_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPI0_SIMO.

(4)

Measured from the termination of the write of new data to the SPI module, In analyzing throughput requirements, additional internal bus

cycles must be accounted for to allow data to be written to the SPI module by the CPU.

Peripheral Information and Electrical Specifications

117

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