TLFD500 datasheet(20/38 Pages) TI1

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TLFD500PN

3.3 V INTEGRATED G.LITE ANALOG FRONT END

SLAS207B – JUNE 1999 – REVISED MAY 2000

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

EQR – equalizer slope and gain control register

Address: 00101b

Contents at reset: 00000000b

Reserved

EQPGA[2]

EQPGA[1]

EQPGA[0]

Reserved

EQ[2]

EQ[1]

EQ[0]

Table 7. EQR Slope and Gain

HEX VALUE

BIT NAME

DESCRIPTION

–

Reserved

Bit reserved for future use

–

0x00

EQPGA[2:0]

0dB

–

0x10

1dB

–

0x20

2dB

–

0x30

3dB

–

0x40

4dB

–

0x50

5dB

–

0x60

6dB

–

0x70

INVALID

–

Reserved

Bit reserved for future use

–

0x00

EQ[2:0]

0dB slope

–

0x01

5dB slope

–

0x02

10dB slope

–

0x03

15dB slope

–

0x04

20dB slope

–

0x05

25dB slope

–

0x06

INVALID

–

0x07

INVALID

NOTES:

6. The formula to convert bit value to EQPGA gain in dB is

EQPGA gain (in dB) = EQPGA[2:0] (in decimal) x 1 dB

Similarly one can compute the EQPGA[2:0] bit combination needed, given the gain in dB.

7. The formula to convert bit value to EQ slope in dB is

EQ slope (in dB/MHz) =EQ[2:0] (in decimal) x 5 dB/MHz

Similarly one can compute the EQ[2:0] bit combination needed, given the slope in dB/MHz.

CAUTION:

Performance of the codec for invalid combination of bits is not guaranteed and such

combinations should not be used. The user should make no assumption that the code bits

will saturate to a maximum or minimum value or wrap around to a valid combination.

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