TLFD500PN

3.3 V INTEGRATED G.LITE ANALOG FRONT END

SLAS207B – JUNE 1999 – REVISED MAY 2000

15

POST OFFICE BOX 655303

BCR – bypass control register

Address: 00001b

Contents at reset: 00000000b

D7

D6

D5

D4

D3

D2

D1

D0

Reserved

Reserved

Reserved

Reserved

ECHO

TXHPEN

RXHP2PD

RXHP1PD

Table 3. EQR Bit Definition

D7

D6

D5

D4

D3

D2

D1

D0

REG. VALUE

BIT NAME

DESCRIPTION

R

–

–

–

–

–

–

–

–

Reserved

Bit reserved for future use

–

R

–

–

–

–

–

–

–

Reserved

Bit reserved for future use

–

–

R

–

–

–

–

–

–

Reserved

Bit reserved for future use

–

–

–

R

–

–

–

–

–

Reserved

Bit reserved for future use

–

–

–

–

0

–

–

–

–

ECHO

Do not echo SDR data on SDX

–

–

–

–

1

–

–

–

0x08

ECHO

Echo SDR data on SDX (see Note 1)

–

–

–

–

–

0

–

–

–

TXHPEN

Enable TX HP Filter

–

–

–

–

–

1

–

–

0x04

TXHPEN

Bypass TX HP Filter

–

–

–

–

–

–

0

–

–

RXHP2PD

Power up RX HP Filter 2

–

–

–

–

–

–

1

–

0x02

RXHP2PD

Power down RX HP Filter 2

–

–

–

–

–

–

–

0

–

RXHP1PD

Power up RX HP Filter 1

–

–

–

–

–

–

–

1

0x01

RXHP1PD

Power down RX HP Filter 1

NOTE 1: ECHO mode allows for a quick verification of the serial interface operation. It sends back the data from input data buffer to the output

data buffer and does not exercise the RX or TX channel.