TLFD500PN

3.3 V INTEGRATED G.LITE ANALOG FRONT END

SLAS207B – JUNE 1999 – REVISED MAY 2000

11

POST OFFICE BOX 655303

detailed description (continued)

SCLK

(Output)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

FSX

(output)

SDX

(Output)

t1 t2 t3

t1: DSP detects FSX

t2: TLFD500PN sends data

t3: DSP latches data

(a) TLFD500PN to DSP

t1: DSP detects FSR

t2: DSP sends data

t3: TLFD500PN latches data

D15

FSR

(output)

SDR

(Input)

t1 t2

t3

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

(b) DSP to TLFD500PN

SCLK

(Output)

NOTE: TI DSP requires 10 ns after the positive edge of the SCLK to give the SDR data. This plus the board delay, output buffer (for SCLK) and

input buffer delay (for SDR) to around 17 ns. As a consequence the SDR data can not be latched at the negative edge of SCLK.

Figure 5. Data Transfers